-#define TRCENA (1 << 24)
-#define VC_HARDERR (1 << 10)
-#define VC_INTERR (1 << 9)
-#define VC_BUSERR (1 << 8)
-#define VC_STATERR (1 << 7)
-#define VC_CHKERR (1 << 6)
-#define VC_NOCPERR (1 << 5)
-#define VC_MMERR (1 << 4)
-#define VC_CORERESET (1 << 0)
-
+#define TRCENA BIT(24)
+#define VC_HARDERR BIT(10)
+#define VC_INTERR BIT(9)
+#define VC_BUSERR BIT(8)
+#define VC_STATERR BIT(7)
+#define VC_CHKERR BIT(6)
+#define VC_NOCPERR BIT(5)
+#define VC_MMERR BIT(4)
+#define VC_CORERESET BIT(0)
+
+/* DCB_DSCSR bit and field definitions */
+#define DSCSR_CDS BIT(16)
+
+/* NVIC registers */