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cortex_m: set the debug reason to DBGRQ when NVIC_DFSR indicates EXTERNAL
[fw/openocd]
/
src
/
target
/
cortex_m.h
diff --git
a/src/target/cortex_m.h
b/src/target/cortex_m.h
index f164e68746ca34d184ded3b24bfc00638702686f..2f29903c8bf66b7607cab00059d3ea7a5848ac49 100644
(file)
--- a/
src/target/cortex_m.h
+++ b/
src/target/cortex_m.h
@@
-22,8
+22,8
@@
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
-#ifndef CORTEX_M_H
-#define CORTEX_M_H
+#ifndef
OPENOCD_TARGET_
CORTEX_M_H
+#define
OPENOCD_TARGET_
CORTEX_M_H
#include "armv7m.h"
#include "armv7m.h"
@@
-48,6
+48,7
@@
#define DWT_CTRL 0xE0001000
#define DWT_CYCCNT 0xE0001004
#define DWT_CTRL 0xE0001000
#define DWT_CYCCNT 0xE0001004
+#define DWT_PCSR 0xE000101C
#define DWT_COMP0 0xE0001020
#define DWT_MASK0 0xE0001024
#define DWT_FUNCTION0 0xE0001028
#define DWT_COMP0 0xE0001020
#define DWT_MASK0 0xE0001024
#define DWT_FUNCTION0 0xE0001028
@@
-126,6
+127,7
@@
#define DFSR_BKPT 2
#define DFSR_DWTTRAP 4
#define DFSR_VCATCH 8
#define DFSR_BKPT 2
#define DFSR_DWTTRAP 4
#define DFSR_VCATCH 8
+#define DFSR_EXTERNAL 16
#define FPCR_CODE 0
#define FPCR_LITERAL 1
#define FPCR_CODE 0
#define FPCR_LITERAL 1
@@
-135,14
+137,14
@@
#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
struct cortex_m_fp_comparator {
#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
struct cortex_m_fp_comparator {
-
int
used;
+
bool
used;
int type;
uint32_t fpcr_value;
uint32_t fpcr_address;
};
struct cortex_m_dwt_comparator {
int type;
uint32_t fpcr_value;
uint32_t fpcr_address;
};
struct cortex_m_dwt_comparator {
-
int
used;
+
bool
used;
uint32_t comp;
uint32_t mask;
uint32_t function;
uint32_t comp;
uint32_t mask;
uint32_t function;
@@
-158,6
+160,7
@@
enum cortex_m_isrmasking_mode {
CORTEX_M_ISRMASK_AUTO,
CORTEX_M_ISRMASK_OFF,
CORTEX_M_ISRMASK_ON,
CORTEX_M_ISRMASK_AUTO,
CORTEX_M_ISRMASK_OFF,
CORTEX_M_ISRMASK_ON,
+ CORTEX_M_ISRMASK_STEPONLY,
};
struct cortex_m_common {
};
struct cortex_m_common {
@@
-171,10
+174,8
@@
struct cortex_m_common {
/* Flash Patch and Breakpoint (FPB) */
int fp_num_lit;
int fp_num_code;
/* Flash Patch and Breakpoint (FPB) */
int fp_num_lit;
int fp_num_code;
- int fp_code_available;
int fp_rev;
int fp_rev;
- int fpb_enabled;
- int auto_bp_type;
+ bool fpb_enabled;
struct cortex_m_fp_comparator *fp_comparator_list;
/* Data Watchpoint and Trace (DWT) */
struct cortex_m_fp_comparator *fp_comparator_list;
/* Data Watchpoint and Trace (DWT) */
@@
-184,10
+185,17
@@
struct cortex_m_common {
struct reg_cache *dwt_cache;
enum cortex_m_soft_reset_config soft_reset_config;
struct reg_cache *dwt_cache;
enum cortex_m_soft_reset_config soft_reset_config;
+ bool vectreset_supported;
enum cortex_m_isrmasking_mode isrmasking_mode;
struct armv7m_common armv7m;
enum cortex_m_isrmasking_mode isrmasking_mode;
struct armv7m_common armv7m;
+
+ int apsel;
+
+ /* Whether this target has the erratum that makes C_MASKINTS not apply to
+ * already pending interrupts */
+ bool maskints_erratum;
};
static inline struct cortex_m_common *
};
static inline struct cortex_m_common *
@@
-210,5
+218,7
@@
void cortex_m_enable_breakpoints(struct target *target);
void cortex_m_enable_watchpoints(struct target *target);
void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target);
void cortex_m_deinit_target(struct target *target);
void cortex_m_enable_watchpoints(struct target *target);
void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target);
void cortex_m_deinit_target(struct target *target);
+int cortex_m_profiling(struct target *target, uint32_t *samples,
+ uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
-#endif /* CORTEX_M_H */
+#endif /*
OPENOCD_TARGET_
CORTEX_M_H */