+ .commands = cortex_a_command_handlers,
+ .target_create = cortex_a_target_create,
+ .init_target = cortex_a_init_target,
+ .examine = cortex_a_examine,
+
+ .read_phys_memory = cortex_a_read_phys_memory,
+ .write_phys_memory = cortex_a_write_phys_memory,
+ .mmu = cortex_a_mmu,
+ .virt2phys = cortex_a_virt2phys,
+};
+
+static const struct command_registration cortex_r4_exec_command_handlers[] = {
+ {
+ .name = "cache_info",
+ .handler = cortex_a_handle_cache_info_command,
+ .mode = COMMAND_EXEC,
+ .help = "display information about target caches",
+ .usage = "",
+ },
+ {
+ .name = "dbginit",
+ .handler = cortex_a_handle_dbginit_command,
+ .mode = COMMAND_EXEC,
+ .help = "Initialize core debug",
+ .usage = "",
+ },
+
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration cortex_r4_command_handlers[] = {
+ {
+ .chain = arm_command_handlers,
+ },
+ {
+ .chain = armv7a_command_handlers,
+ },
+ {
+ .name = "cortex_r4",
+ .mode = COMMAND_ANY,
+ .help = "Cortex-R4 command group",
+ .usage = "",
+ .chain = cortex_r4_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct target_type cortexr4_target = {
+ .name = "cortex_r4",
+
+ .poll = cortex_a_poll,
+ .arch_state = armv7a_arch_state,
+
+ .halt = cortex_a_halt,
+ .resume = cortex_a_resume,
+ .step = cortex_a_step,
+
+ .assert_reset = cortex_a_assert_reset,
+ .deassert_reset = cortex_a_deassert_reset,
+
+ /* REVISIT allow exporting VFP3 registers ... */
+ .get_gdb_reg_list = arm_get_gdb_reg_list,
+
+ .read_memory = cortex_a_read_memory,
+ .write_memory = cortex_a_write_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
+
+ .run_algorithm = armv4_5_run_algorithm,
+
+ .add_breakpoint = cortex_a_add_breakpoint,
+ .add_context_breakpoint = cortex_a_add_context_breakpoint,
+ .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint,
+ .remove_breakpoint = cortex_a_remove_breakpoint,
+ .add_watchpoint = NULL,
+ .remove_watchpoint = NULL,