+#define ARMV8_MSR_IM(op1, crm, op2) \
+ (0xd500401f | ((op1) << 16) | ((crm) << 8) | ((op2) << 5))
+
+#define ARMV8_MRS_T1(r, m1, rd, m) (0xF3E08020 | (r << 20) | (m1 << 16) | (rd << 8) | (m << 4))
+#define ARMV8_MRS_XPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
+#define ARMV8_MSR_GP_T1(r, m1, rd, m) (0xF3808020 | (r << 20) | (m1 << 8) | (rd << 16) | (m << 4))
+#define ARMV8_MSR_GP_XPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
+
+#define ARMV8_BKPT(im) (0xD4200000 | ((im & 0xffff) << 5))
+#define ARMV8_HLT(im) (0x0D4400000 | ((im & 0xffff) << 5))
+#define ARMV8_HLT_A1(im) (0xE1000070 | ((im & 0xFFF0) << 4) | (im & 0xF))
+#define ARMV8_HLT_T1(im) (0xba80 | (im & 0x3f))
+
+#define ARMV8_MOVFSP_64(rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (rt))
+#define ARMV8_MOVTSP_64(rt) ((1 << 31) | 0x11000000 | (rt << 5) | (0x1F))
+#define ARMV8_MOVFSP_32(rt) (0x11000000 | (0x1f << 5) | (rt))
+#define ARMV8_MOVTSP_32(rt) (0x11000000 | (rt << 5) | (0x1F))
+
+#define ARMV8_LDRB_IP(rd, rn) (0x38401400 | (rn << 5) | rd)
+#define ARMV8_LDRH_IP(rd, rn) (0x78402400 | (rn << 5) | rd)
+#define ARMV8_LDRW_IP(rd, rn) (0xb8404400 | (rn << 5) | rd)
+
+#define ARMV8_LDRB_IP_T3(rd, rn) (0xf8100b01 | (rn << 16) | (rd << 12))
+#define ARMV8_LDRH_IP_T3(rd, rn) (0xf8300b02 | (rn << 16) | (rd << 12))
+#define ARMV8_LDRW_IP_T3(rd, rn) (0xf8500b04 | (rn << 16) | (rd << 12))
+
+#define ARMV8_STRB_IP(rd, rn) (0x38001400 | (rn << 5) | rd)
+#define ARMV8_STRH_IP(rd, rn) (0x78002400 | (rn << 5) | rd)
+#define ARMV8_STRW_IP(rd, rn) (0xb8004400 | (rn << 5) | rd)