- /* get or set register through cache, return error if target is running and synchronisation is impossible */
- int (*get_core_reg_32)(struct target_s *target, int num, u32* value);
- int (*set_core_reg_32)(struct target_s *target, int num, u32 value);
-
- arm_jtag_t jtag_info;
- reg_cache_t *eice_cache;
- reg_cache_t *etm_cache;
-
- int (*examine_debug_reason)(target_t *target);
-
- void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
-
-// void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
-// void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
-// void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
-
-/*
- void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
-
- void (*load_word_regs)(target_t *target, u32 mask);
- void (*load_hword_reg)(target_t *target, int num);
- void (*load_byte_reg)(target_t *target, int num);
-
- void (*store_word_regs)(target_t *target, u32 mask);
- void (*store_hword_reg)(target_t *target, int num);
- void (*store_byte_reg)(target_t *target, int num);