+struct armv7a_cachesize {
+ uint32_t level_num;
+ /* cache dimensionning */
+ uint32_t linelen;
+ uint32_t associativity;
+ uint32_t nsets;
+ uint32_t cachesize;
+ /* info for set way operation on cache */
+ uint32_t index;
+ uint32_t index_shift;
+ uint32_t way;
+ uint32_t way_shift;
+};
+
+struct armv7a_cache_common {
+ int ctype;
+ struct armv7a_cachesize d_u_size; /* data cache */
+ struct armv7a_cachesize i_size; /* instruction cache */
+ int i_cache_enabled;
+ int d_u_cache_enabled;
+ /* l2 external unified cache if some */
+ void *l2_cache;
+ int (*flush_all_data_cache)(struct target *target);
+ int (*display_cache_info)(struct command_context *cmd_ctx,
+ struct armv7a_cache_common *armv7a_cache);
+};
+
+struct armv7a_mmu_common {
+ /* following field mmu working way */
+ int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
+ uint32_t ttbr0_mask;/* masked to be used */
+ uint32_t os_border;
+
+ int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer);
+ struct armv7a_cache_common armv7a_cache;
+ uint32_t mmu_enabled;
+};
+
+struct armv7a_common {
+ struct arm arm;