+/* See ARMv7a arch spec DDI 0406C C11.10 */
+#define CPUDBG_ID_PFR1 0xD24
+
+/* Masks for Vector Catch register */
+#define DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7))
+#define DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6))
+#define DBG_VCR_DATA_ABORT_MASK ((1 << 28) | (1 << 4))
+#define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
+#define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2))
+
+/* Masks for Multiprocessor Affinity Register */
+#define MPIDR_MP_EXT (1UL << 31)
+