-/* map linear number to mode bits */
-static inline enum armv7a_mode armv7a_number_to_mode(int number)
-{
- switch(number)
- {
- case 0: return ARMV7A_MODE_USR; break;
- case 1: return ARMV7A_MODE_FIQ; break;
- case 2: return ARMV7A_MODE_IRQ; break;
- case 3: return ARMV7A_MODE_SVC; break;
- case 4: return ARMV7A_MODE_ABT; break;
- case 5: return ARMV7A_MODE_UND; break;
- case 6: return ARMV7A_MODE_SYS; break;
- case 7: return ARMV7A_MODE_MON; break;
- default:
- LOG_ERROR("mode index out of bounds");
- return ARMV7A_MODE_ANY;
- }
-};
+/* See ARMv7a arch spec section C10.7 */
+#define CPUDBG_DSCCR 0x028
+#define CPUDBG_DSMCR 0x02C
+
+/* See ARMv7a arch spec section C10.8 */
+#define CPUDBG_AUTHSTATUS 0xFB8
+
+/* See ARMv7a arch spec DDI 0406C C11.10 */
+#define CPUDBG_ID_PFR1 0xD24
+
+/* Masks for Vector Catch register */
+#define DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7))
+#define DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6))
+#define DBG_VCR_DATA_ABORT_MASK ((1 << 28) | (1 << 4))
+#define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
+#define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2))
+
+/* Masks for Multiprocessor Affinity Register */
+#define MPIDR_MP_EXT (1UL << 31)
+
+int armv7a_arch_state(struct target *target);
+int armv7a_identify_cache(struct target *target);
+int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
+
+int armv7a_handle_cache_info_command(struct command_invocation *cmd,
+ struct armv7a_cache_common *armv7a_cache);
+int armv7a_read_ttbcr(struct target *target);