+struct armv7a_cachesize {
+ /* cache dimensioning */
+ uint32_t linelen;
+ uint32_t associativity;
+ uint32_t nsets;
+ uint32_t cachesize;
+ /* info for set way operation on cache */
+ uint32_t index;
+ uint32_t index_shift;
+ uint32_t way;
+ uint32_t way_shift;
+};
+
+/* information about one architecture cache at any level */
+struct armv7a_arch_cache {
+ int ctype; /* cache type, CLIDR encoding */
+ struct armv7a_cachesize d_u_size; /* data cache */
+ struct armv7a_cachesize i_size; /* instruction cache */
+};
+
+/* common cache information */
+struct armv7a_cache_common {
+ int info; /* -1 invalid, else valid */
+ int loc; /* level of coherency */
+ uint32_t dminline; /* minimum d-cache linelen */
+ uint32_t iminline; /* minimum i-cache linelen */
+ struct armv7a_arch_cache arch[6]; /* cache info, L1 - L7 */
+ int i_cache_enabled;
+ int d_u_cache_enabled;
+ int auto_cache_enabled; /* openocd automatic
+ * cache handling */
+ /* outer unified cache if some */
+ void *outer_cache;
+ int (*flush_all_data_cache)(struct target *target);
+};
+
+struct armv7a_mmu_common {
+ /* following field mmu working way */
+ int32_t cached; /* 0: not initialized, 1: initialized */
+ uint32_t ttbcr; /* cache for ttbcr register */
+ uint32_t ttbr[2];
+ uint32_t ttbr_mask[2];
+ uint32_t ttbr_range[2];
+
+ int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer);
+ struct armv7a_cache_common armv7a_cache;
+ uint32_t mmu_enabled;
+};
+
+struct armv7a_common {
+ struct arm arm;