projects
/
fw
/
openocd
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
flash: use proper format with uint32_t
[fw/openocd]
/
src
/
target
/
armv4_5_mmu.c
diff --git
a/src/target/armv4_5_mmu.c
b/src/target/armv4_5_mmu.c
index 8978f354dafa9c5b01ed7ab31e4b7fb4021850c4..115a489503e1e1f7f11e613c5a543dd21073cd2d 100644
(file)
--- a/
src/target/armv4_5_mmu.c
+++ b/
src/target/armv4_5_mmu.c
@@
-13,10
+13,9
@@
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@
-25,8
+24,8
@@
#include "target.h"
#include "armv4_5_mmu.h"
#include "target.h"
#include "armv4_5_mmu.h"
-
-
int armv4_5_mmu_translate_va(struct target *target,
struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
+int armv4_5_mmu_translate_va(struct target *target,
+
struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
{
uint32_t first_lvl_descriptor = 0x0;
uint32_t second_lvl_descriptor = 0x0;
{
uint32_t first_lvl_descriptor = 0x0;
uint32_t second_lvl_descriptor = 0x0;
@@
-34,62
+33,55
@@
int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
int retval;
retval = armv4_5_mmu->get_ttb(target, &ttb);
if (retval != ERROR_OK)
int retval;
retval = armv4_5_mmu->get_ttb(target, &ttb);
if (retval != ERROR_OK)
- return retval;
+
return retval;
retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
(ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
(ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
- 4, 1, (uint8_t*)&first_lvl_descriptor);
+ 4, 1, (uint8_t
*)&first_lvl_descriptor);
if (retval != ERROR_OK)
if (retval != ERROR_OK)
- return retval;
- first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
+
return retval;
+ first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t
*)&first_lvl_descriptor);
LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
- if ((first_lvl_descriptor & 0x3) == 0)
- {
+ if ((first_lvl_descriptor & 0x3) == 0) {
LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
- if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
- {
+ if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) {
LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
- if ((first_lvl_descriptor & 0x3) == 2)
- {
+ if ((first_lvl_descriptor & 0x3) == 2) {
/* section descriptor */
*cb = (first_lvl_descriptor & 0xc) >> 2;
*val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
return ERROR_OK;
}
/* section descriptor */
*cb = (first_lvl_descriptor & 0xc) >> 2;
*val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
return ERROR_OK;
}
- if ((first_lvl_descriptor & 0x3) == 1)
- {
+ if ((first_lvl_descriptor & 0x3) == 1) {
/* coarse page table */
retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
(first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
/* coarse page table */
retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
(first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
- 4, 1, (uint8_t*)&second_lvl_descriptor);
+ 4, 1, (uint8_t
*)&second_lvl_descriptor);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- }
- else if ((first_lvl_descriptor & 0x3) == 3)
- {
+ } else if ((first_lvl_descriptor & 0x3) == 3) {
/* fine page table */
retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
(first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
/* fine page table */
retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
(first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
- 4, 1, (uint8_t*)&second_lvl_descriptor);
+ 4, 1, (uint8_t
*)&second_lvl_descriptor);
if (retval != ERROR_OK)
return retval;
}
if (retval != ERROR_OK)
return retval;
}
- second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
+ second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t
*)&second_lvl_descriptor);
LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
- if ((second_lvl_descriptor & 0x3) == 0)
- {
+ if ((second_lvl_descriptor & 0x3) == 0) {
LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
@@
-97,22
+89,19
@@
int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
/* cacheable/bufferable is always specified in bits 3-2 */
*cb = (second_lvl_descriptor & 0xc) >> 2;
/* cacheable/bufferable is always specified in bits 3-2 */
*cb = (second_lvl_descriptor & 0xc) >> 2;
- if ((second_lvl_descriptor & 0x3) == 1)
- {
+ if ((second_lvl_descriptor & 0x3) == 1) {
/* large page descriptor */
*val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
return ERROR_OK;
}
/* large page descriptor */
*val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
return ERROR_OK;
}
- if ((second_lvl_descriptor & 0x3) == 2)
- {
+ if ((second_lvl_descriptor & 0x3) == 2) {
/* small page descriptor */
*val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
return ERROR_OK;
}
/* small page descriptor */
*val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
return ERROR_OK;
}
- if ((second_lvl_descriptor & 0x3) == 3)
- {
+ if ((second_lvl_descriptor & 0x3) == 3) {
/* tiny page descriptor */
*val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
return ERROR_OK;
/* tiny page descriptor */
*val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
return ERROR_OK;
@@
-123,7
+112,9
@@
int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
return ERROR_TARGET_TRANSLATION_FAULT;
}
return ERROR_TARGET_TRANSLATION_FAULT;
}
-int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int armv4_5_mmu_read_physical(struct target *target,
+ struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address,
+ uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
{
int retval;
@@
-132,24
+123,26
@@
int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *
/* disable MMU and data (or unified) cache */
retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
/* disable MMU and data (or unified) cache */
retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
- if (retval !=ERROR_OK)
+ if (retval !=
ERROR_OK)
return retval;
retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
return retval;
retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
- if (retval !=ERROR_OK)
+ if (retval !=
ERROR_OK)
return retval;
/* reenable MMU / cache */
retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
armv4_5_mmu->armv4_5_cache.i_cache_enabled);
return retval;
/* reenable MMU / cache */
retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
armv4_5_mmu->armv4_5_cache.i_cache_enabled);
- if (retval !=ERROR_OK)
+ if (retval !=
ERROR_OK)
return retval;
return retval;
}
return retval;
return retval;
}
-int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int armv4_5_mmu_write_physical(struct target *target,
+ struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address,
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;
{
int retval;
@@
-158,18
+151,18
@@
int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common
/* disable MMU and data (or unified) cache */
retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
/* disable MMU and data (or unified) cache */
retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
- if (retval !=ERROR_OK)
+ if (retval !=
ERROR_OK)
return retval;
retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
return retval;
retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
- if (retval !=ERROR_OK)
+ if (retval !=
ERROR_OK)
return retval;
/* reenable MMU / cache */
retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
armv4_5_mmu->armv4_5_cache.i_cache_enabled);
return retval;
/* reenable MMU / cache */
retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
armv4_5_mmu->armv4_5_cache.i_cache_enabled);
- if (retval !=ERROR_OK)
+ if (retval !=
ERROR_OK)
return retval;
return retval;
return retval;
return retval;