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change #include "arm_jtag.h" to <target/arm_jtag.h>
[fw/openocd]
/
src
/
target
/
armv4_5_cache.h
diff --git
a/src/target/armv4_5_cache.h
b/src/target/armv4_5_cache.h
index 766718b6a7f9409b7868563fd78601a65aba9e09..c529b458413345f80f668de6b51eb1a84ec5b933 100644
(file)
--- a/
src/target/armv4_5_cache.h
+++ b/
src/target/armv4_5_cache.h
@@
-20,30
+20,42
@@
#ifndef ARMV4_5_CACHE_H
#define ARMV4_5_CACHE_H
#ifndef ARMV4_5_CACHE_H
#define ARMV4_5_CACHE_H
-#include "types.h"
-#include "command.h"
+#include <helper/types.h>
-typedef struct armv4_5_cachesize_s
+struct command_context;
+
+struct armv4_5_cachesize
{
int linelen;
int associativity;
int nsets;
int cachesize;
{
int linelen;
int associativity;
int nsets;
int cachesize;
-}
armv4_5_cachesize_t
;
+};
-typedef struct armv4_5_cache_common_s
+struct armv4_5_cache_common
{
int ctype; /* specify supported cache operations */
int separate; /* separate caches or unified cache */
{
int ctype; /* specify supported cache operations */
int separate; /* separate caches or unified cache */
-
armv4_5_cachesize_t d_u_size;
/* data cache */
-
armv4_5_cachesize_t
i_size; /* instruction cache */
+
struct armv4_5_cachesize d_u_size;
/* data cache */
+
struct armv4_5_cachesize
i_size; /* instruction cache */
int i_cache_enabled;
int d_u_cache_enabled;
int i_cache_enabled;
int d_u_cache_enabled;
-} armv4_5_cache_common_t;
+};
+
+int armv4_5_identify_cache(uint32_t cache_type_reg,
+ struct armv4_5_cache_common *cache);
+int armv4_5_cache_state(uint32_t cp15_control_reg,
+ struct armv4_5_cache_common *cache);
-extern int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache);
-
extern int armv4_5_cache_state(u32 cp15_control_reg, armv4_5_cache_common_t *
cache);
+int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx,
+
struct armv4_5_cache_common *armv4_5_
cache);
-extern int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx, armv4_5_cache_common_t *armv4_5_cache);
+enum
+{
+ ARMV4_5_D_U_CACHE_ENABLED = 0x4,
+ ARMV4_5_I_CACHE_ENABLED = 0x1000,
+ ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,
+ ARMV4_5_CACHE_RR_BIT = 0x5000,
+};
#endif /* ARMV4_5_CACHE_H */
#endif /* ARMV4_5_CACHE_H */