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ARM: call thumb_pass_branch_condition() only for actual branch opcodes
[fw/openocd]
/
src
/
target
/
arm_simulator.c
diff --git
a/src/target/arm_simulator.c
b/src/target/arm_simulator.c
index e2f49c390331dbc988178d9159e7850c702b0e9a..646baea70764a6359cd4f2368432641240814d60 100644
(file)
--- a/
src/target/arm_simulator.c
+++ b/
src/target/arm_simulator.c
@@
-309,19
+309,17
@@
int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
{
uint16_t opcode;
{
uint16_t opcode;
- if ((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK)
- {
+ retval = target_read_u16(target, current_pc, &opcode);
+ if (retval != ERROR_OK)
return retval;
return retval;
- }
- if ((retval = thumb_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
- {
+ retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
+ if (retval != ERROR_OK)
return retval;
return retval;
- }
instruction_size = 2;
/* check condition code (only for branch instructions) */
instruction_size = 2;
/* check condition code (only for branch instructions) */
- if (
(!thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode))
&&
-
(instruction.type == ARM_B
))
+ if (
instruction.type == ARM_B
&&
+
!thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode
))
{
if (dry_run_pc)
{
{
if (dry_run_pc)
{