- /* return value in R0 */
- buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
- armv4_5->core_cache->reg_list[0].dirty = 1;
+ /* REVISIT this looks wrong ... ARM11 and Cortex-A8
+ * should work this way at least sometimes.
+ */
+ if (is_arm7_9(target_to_arm7_9(target)))
+ {
+ uint32_t spsr;
+
+ /* return value in R0 */
+ buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, result);
+ arm->core_cache->reg_list[0].dirty = 1;
+
+ /* LR --> PC */
+ buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32,
+ buf_get_u32(arm_reg_current(arm,14)->value, 0, 32));
+ arm->core_cache->reg_list[15].dirty = 1;