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flash/nor/nrf5: fix protection setting on nRF51
[fw/openocd]
/
src
/
target
/
arm_opcodes.h
diff --git
a/src/target/arm_opcodes.h
b/src/target/arm_opcodes.h
index 482abe630a0025464427e7f1475df4b631507793..90f8416000c154b40791a6fa86434217693e0ea5 100644
(file)
--- a/
src/target/arm_opcodes.h
+++ b/
src/target/arm_opcodes.h
@@
-38,7
+38,7
@@
/* Store multiple increment after
* Rn: base register
* List: for each bit in list: store register
/* Store multiple increment after
* Rn: base register
* List: for each bit in list: store register
- * S: in privile
d
ged mode: store user-mode registers
+ * S: in privileged mode: store user-mode registers
* W = 1: update the base register. W = 0: leave the base register untouched
*/
#define ARMV4_5_STMIA(Rn, List, S, W) \
* W = 1: update the base register. W = 0: leave the base register untouched
*/
#define ARMV4_5_STMIA(Rn, List, S, W) \
@@
-47,7
+47,7
@@
/* Load multiple increment after
* Rn: base register
* List: for each bit in list: store register
/* Load multiple increment after
* Rn: base register
* List: for each bit in list: store register
- * S: in privile
d
ged mode: store user-mode registers
+ * S: in privileged mode: store user-mode registers
* W = 1: update the base register. W = 0: leave the base register untouched
*/
#define ARMV4_5_LDMIA(Rn, List, S, W) \
* W = 1: update the base register. W = 0: leave the base register untouched
*/
#define ARMV4_5_LDMIA(Rn, List, S, W) \
@@
-213,7
+213,7
@@
/* Breakpoint instruction (ARMv5)
* Im: 16-bit immediate
*/
/* Breakpoint instruction (ARMv5)
* Im: 16-bit immediate
*/
-#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) <<
8
) | (Im & 0xf))
+#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) <<
4
) | (Im & 0xf))
/* Thumb mode instructions
/* Thumb mode instructions