-
-/* load/store dual or exclusive, table branch */
-static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address,
- struct arm_instruction *instruction, char *cp)
-{
- unsigned op1op2 = (opcode >> 20) & 0x3;
- unsigned op3 = (opcode >> 4) & 0xf;
- char *mnemonic;
- unsigned rn = (opcode >> 16) & 0xf;
- unsigned rt = (opcode >> 12) & 0xf;
- unsigned rd = (opcode >> 8) & 0xf;
- unsigned imm = opcode & 0xff;
- char *p1 = "";
- char *p2 = "]";
-
- op1op2 |= (opcode >> 21) & 0xc;
- switch (op1op2) {
- case 0:
- mnemonic = "STREX";
- goto strex;
- case 1:
- mnemonic = "LDREX";
- goto ldrex;
- case 2:
- case 6:
- case 8:
- case 10:
- case 12:
- case 14:
- mnemonic = "STRD";
- goto immediate;
- case 3:
- case 7:
- case 9:
- case 11:
- case 13:
- case 15:
- mnemonic = "LDRD";
- if (rn == 15)
- goto literal;
- else
- goto immediate;
- case 4:
- switch (op3) {
- case 4:
- mnemonic = "STREXB";
- break;
- case 5:
- mnemonic = "STREXH";
- break;
- default:
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
- rd = opcode & 0xf;
- imm = 0;
- goto strex;
- case 5:
- switch (op3) {
- case 0:
- sprintf(cp, "TBB\t[r%u, r%u]", rn, imm & 0xf);
- return ERROR_OK;
- case 1:
- sprintf(cp, "TBH\t[r%u, r%u, LSL #1]", rn, imm & 0xf);
- return ERROR_OK;
- case 4:
- mnemonic = "LDREXB";
- break;
- case 5:
- mnemonic = "LDREXH";
- break;
- default:
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
- imm = 0;
- goto ldrex;
- }
- return ERROR_COMMAND_SYNTAX_ERROR;
-
-strex:
- imm <<= 2;
- if (imm)
- sprintf(cp, "%s\tr%u, r%u, [r%u, #%u]\t; %#2.2x",
- mnemonic, rd, rt, rn, imm, imm);
- else
- sprintf(cp, "%s\tr%u, r%u, [r%u]",
- mnemonic, rd, rt, rn);
- return ERROR_OK;
-
-ldrex:
- imm <<= 2;
- if (imm)
- sprintf(cp, "%s\tr%u, [r%u, #%u]\t; %#2.2x",
- mnemonic, rt, rn, imm, imm);
- else
- sprintf(cp, "%s\tr%u, [r%u]",
- mnemonic, rt, rn);
- return ERROR_OK;
-
-immediate:
- /* two indexed modes will write back rn */
- if (opcode & (1 << 21)) {
- if (opcode & (1 << 24)) /* pre-indexed */
- p2 = "]!";
- else { /* post-indexed */
- p1 = "]";
- p2 = "";
- }
- }
-
- imm <<= 2;
- sprintf(cp, "%s\tr%u, r%u, [r%u%s, #%s%u%s\t; %#2.2x",
- mnemonic, rt, rd, rn, p1,
- (opcode & (1 << 23)) ? "" : "-",
- imm, p2, imm);
- return ERROR_OK;
-
-literal:
- address = thumb_alignpc4(address);
- imm <<= 2;
- if (opcode & (1 << 23))
- address += imm;
- else
- address -= imm;
- sprintf(cp, "%s\tr%u, r%u, %#8.8" PRIx32,
- mnemonic, rt, rd, address);
- return ERROR_OK;
-}
-
-static int t2ev_data_shift(uint32_t opcode, uint32_t address,
- struct arm_instruction *instruction, char *cp)
-{
- int op = (opcode >> 21) & 0xf;
- int rd = (opcode >> 8) & 0xf;
- int rn = (opcode >> 16) & 0xf;
- int type = (opcode >> 4) & 0x3;
- int immed = (opcode >> 6) & 0x3;
- char *mnemonic;
- char *suffix = "";
-
- immed |= (opcode >> 10) & 0x1c;
- if (opcode & (1 << 20))
- suffix = "S";
-
- switch (op) {
- case 0:
- if (rd == 0xf) {
- if (!(opcode & (1 << 20)))
- return ERROR_COMMAND_SYNTAX_ERROR;
- instruction->type = ARM_TST;
- mnemonic = "TST";
- suffix = "";
- goto two;
- }
- instruction->type = ARM_AND;
- mnemonic = "AND";
- break;
- case 1:
- instruction->type = ARM_BIC;
- mnemonic = "BIC";
- break;
- case 2:
- if (rn == 0xf) {
- instruction->type = ARM_MOV;
- switch (type) {
- case 0:
- if (immed == 0) {
- sprintf(cp, "MOV%s.W\tr%d, r%d",
- suffix, rd,
- (int) (opcode & 0xf));
- return ERROR_OK;
- }
- mnemonic = "LSL";
- break;
- case 1:
- mnemonic = "LSR";
- break;
- case 2:
- mnemonic = "ASR";
- break;
- default:
- if (immed == 0) {
- sprintf(cp, "RRX%s\tr%d, r%d",
- suffix, rd,
- (int) (opcode & 0xf));
- return ERROR_OK;
- }
- mnemonic = "ROR";
- break;
- }
- goto immediate;
- } else {
- instruction->type = ARM_ORR;
- mnemonic = "ORR";
- }
- break;
- case 3:
- if (rn == 0xf) {
- instruction->type = ARM_MVN;
- mnemonic = "MVN";
- rn = rd;
- goto two;
- } else {
- /* instruction->type = ARM_ORN; */
- mnemonic = "ORN";
- }
- break;
- case 4:
- if (rd == 0xf) {
- if (!(opcode & (1 << 20)))
- return ERROR_COMMAND_SYNTAX_ERROR;
- instruction->type = ARM_TEQ;
- mnemonic = "TEQ";
- suffix = "";
- goto two;
- }
- instruction->type = ARM_EOR;
- mnemonic = "EOR";
- break;
- case 8:
- if (rd == 0xf) {
- if (!(opcode & (1 << 20)))
- return ERROR_COMMAND_SYNTAX_ERROR;
- instruction->type = ARM_CMN;
- mnemonic = "CMN";
- suffix = "";
- goto two;
- }
- instruction->type = ARM_ADD;
- mnemonic = "ADD";
- break;
- case 0xa:
- instruction->type = ARM_ADC;
- mnemonic = "ADC";
- break;
- case 0xb:
- instruction->type = ARM_SBC;
- mnemonic = "SBC";
- break;
- case 0xd:
- if (rd == 0xf) {
- if (!(opcode & (1 << 21)))
- return ERROR_COMMAND_SYNTAX_ERROR;
- instruction->type = ARM_CMP;
- mnemonic = "CMP";
- suffix = "";
- goto two;
- }
- instruction->type = ARM_SUB;
- mnemonic = "SUB";
- break;
- case 0xe:
- instruction->type = ARM_RSB;
- mnemonic = "RSB";
- break;
- default:
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- sprintf(cp, "%s%s.W\tr%d, r%d, r%d",
- mnemonic, suffix, rd, rn, (int) (opcode & 0xf));
-
-shift:
- cp = strchr(cp, 0);
-
- switch (type) {
- case 0:
- if (immed == 0)
- return ERROR_OK;
- suffix = "LSL";
- break;
- case 1:
- suffix = "LSR";
- if (immed == 32)
- immed = 0;
- break;
- case 2:
- suffix = "ASR";
- if (immed == 32)
- immed = 0;
- break;
- case 3:
- if (immed == 0) {
- strcpy(cp, ", RRX");
- return ERROR_OK;
- }
- suffix = "ROR";
- break;
- }
- sprintf(cp, ", %s #%d", suffix, immed ? immed : 32);
- return ERROR_OK;
-
-two:
- sprintf(cp, "%s%s.W\tr%d, r%d",
- mnemonic, suffix, rn, (int) (opcode & 0xf));
- goto shift;
-
-immediate:
- sprintf(cp, "%s%s.W\tr%d, r%d, #%d",
- mnemonic, suffix, rd,
- (int) (opcode & 0xf), immed ? immed : 32);
- return ERROR_OK;
-}
-
-static int t2ev_data_reg(uint32_t opcode, uint32_t address,
- struct arm_instruction *instruction, char *cp)
-{
- char *mnemonic;
- char *suffix = "";
-
- if (((opcode >> 4) & 0xf) == 0) {
- switch ((opcode >> 21) & 0x7) {
- case 0:
- mnemonic = "LSL";
- break;
- case 1:
- mnemonic = "LSR";
- break;
- case 2:
- mnemonic = "ASR";
- break;
- case 3:
- mnemonic = "ROR";
- break;
- default:
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- instruction->type = ARM_MOV;
- if (opcode & (1 << 20))
- suffix = "S";
- sprintf(cp, "%s%s.W\tr%d, r%d, r%d",
- mnemonic, suffix,
- (int) (opcode >> 8) & 0xf,
- (int) (opcode >> 16) & 0xf,
- (int) (opcode >> 0) & 0xf);
-
- } else if (opcode & (1 << 7)) {
- switch ((opcode >> 20) & 0xf) {
- case 0:
- case 1:
- case 4:
- case 5:
- switch ((opcode >> 4) & 0x3) {
- case 1:
- suffix = ", ROR #8";
- break;
- case 2:
- suffix = ", ROR #16";
- break;
- case 3:
- suffix = ", ROR #24";
- break;
- }
- sprintf(cp, "%cXT%c.W\tr%d, r%d%s",
- (opcode & (1 << 24)) ? 'U' : 'S',
- (opcode & (1 << 26)) ? 'B' : 'H',
- (int) (opcode >> 8) & 0xf,
- (int) (opcode >> 0) & 0xf,
- suffix);
- break;
- case 8:
- case 9:
- case 0xa:
- case 0xb:
- if (opcode & (1 << 6))
- return ERROR_COMMAND_SYNTAX_ERROR;
- if (((opcode >> 12) & 0xf) != 0xf)
- return ERROR_COMMAND_SYNTAX_ERROR;
- if (!(opcode & (1 << 20)))
- return ERROR_COMMAND_SYNTAX_ERROR;
-
- switch (((opcode >> 19) & 0x04)
- | ((opcode >> 4) & 0x3)) {
- case 0:
- mnemonic = "REV.W";
- break;
- case 1:
- mnemonic = "REV16.W";
- break;
- case 2:
- mnemonic = "RBIT";
- break;
- case 3:
- mnemonic = "REVSH.W";
- break;
- case 4:
- mnemonic = "CLZ";
- break;
- default:
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
- sprintf(cp, "%s\tr%d, r%d",
- mnemonic,
- (int) (opcode >> 8) & 0xf,
- (int) (opcode >> 0) & 0xf);
- break;
- default:
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
- }
-
- return ERROR_OK;
-}
-
-static int t2ev_load_word(uint32_t opcode, uint32_t address,
- struct arm_instruction *instruction, char *cp)
-{
- int rn = (opcode >> 16) & 0xf;
- int immed;
-
- instruction->type = ARM_LDR;
-
- if (rn == 0xf) {
- immed = opcode & 0x0fff;
- if ((opcode & (1 << 23)) == 0)
- immed = -immed;
- sprintf(cp, "LDR\tr%d, %#8.8" PRIx32,
- (int) (opcode >> 12) & 0xf,
- thumb_alignpc4(address) + immed);
- return ERROR_OK;
- }
-
- if (opcode & (1 << 23)) {
- immed = opcode & 0x0fff;
- sprintf(cp, "LDR.W\tr%d, [r%d, #%d]\t; %#3.3x",
- (int) (opcode >> 12) & 0xf,
- rn, immed, immed);
- return ERROR_OK;
- }
-
- if (!(opcode & (0x3f << 6))) {
- sprintf(cp, "LDR.W\tr%d, [r%d, r%d, LSL #%d]",
- (int) (opcode >> 12) & 0xf,
- rn,
- (int) (opcode >> 0) & 0xf,
- (int) (opcode >> 4) & 0x3);
- return ERROR_OK;
- }
-
-
- if (((opcode >> 8) & 0xf) == 0xe) {
- immed = opcode & 0x00ff;
-
- sprintf(cp, "LDRT\tr%d, [r%d, #%d]\t; %#2.2x",
- (int) (opcode >> 12) & 0xf,
- rn, immed, immed);
- return ERROR_OK;
- }
-
- if (((opcode >> 8) & 0xf) == 0xc || (opcode & 0x0900) == 0x0900) {
- char *p1 = "]", *p2 = "";
-
- if (!(opcode & 0x0500))
- return ERROR_COMMAND_SYNTAX_ERROR;
-
- immed = opcode & 0x00ff;
-
- /* two indexed modes will write back rn */
- if (opcode & 0x100) {
- if (opcode & 0x400) /* pre-indexed */
- p2 = "]!";
- else { /* post-indexed */
- p1 = "]";
- p2 = "";
- }
- }
-
- sprintf(cp, "LDR\tr%d, [r%d%s, #%s%u%s\t; %#2.2x",
- (int) (opcode >> 12) & 0xf,
- rn, p1,
- (opcode & 0x200) ? "" : "-",
- immed, p2, immed);
- return ERROR_OK;
- }
-
- return ERROR_COMMAND_SYNTAX_ERROR;
-}
-
-static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address,
- struct arm_instruction *instruction, char *cp)
-{
- int rn = (opcode >> 16) & 0xf;
- int rt = (opcode >> 12) & 0xf;
- int op2 = (opcode >> 6) & 0x3f;
- unsigned immed;
- char *p1 = "", *p2 = "]";
- char *mnemonic;
-
- switch ((opcode >> 23) & 0x3) {
- case 0:
- if ((rn & rt) == 0xf) {
-pld_literal:
- immed = opcode & 0xfff;
- address = thumb_alignpc4(address);
- if (opcode & (1 << 23))
- address += immed;
- else
- address -= immed;
- sprintf(cp, "PLD\tr%d, %#8.8" PRIx32,
- rt, address);
- return ERROR_OK;
- }
- if (rn == 0x0f && rt != 0x0f) {
-ldrb_literal:
- immed = opcode & 0xfff;
- address = thumb_alignpc4(address);
- if (opcode & (1 << 23))
- address += immed;
- else
- address -= immed;
- sprintf(cp, "LDRB\tr%d, %#8.8" PRIx32,
- rt, address);
- return ERROR_OK;
- }
- if (rn == 0x0f)
- break;
- if ((op2 & 0x3c) == 0x38) {
- immed = opcode & 0xff;
- sprintf(cp, "LDRBT\tr%d, [r%d, #%d]\t; %#2.2x",
- rt, rn, immed, immed);
- return ERROR_OK;
- }
- if ((op2 & 0x3c) == 0x30) {
- if (rt == 0x0f) {
- immed = opcode & 0xff;
- immed = -immed;
-preload_immediate:
- p1 = (opcode & (1 << 21)) ? "W" : "";
- sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
- p1, rn, immed, immed);
- return ERROR_OK;
- }
- mnemonic = "LDRB";
-ldrxb_immediate_t3:
- immed = opcode & 0xff;
- if (!(opcode & 0x200))
- immed = -immed;
-
- /* two indexed modes will write back rn */
- if (opcode & 0x100) {
- if (opcode & 0x400) /* pre-indexed */
- p2 = "]!";
- else { /* post-indexed */
- p1 = "]";
- p2 = "";
- }
- }
-ldrxb_immediate_t2:
- sprintf(cp, "%s\tr%d, [r%d%s, #%d%s\t; %#8.8x",
- mnemonic, rt, rn, p1,
- immed, p2, immed);
- return ERROR_OK;
- }
- if ((op2 & 0x24) == 0x24) {
- mnemonic = "LDRB";
- goto ldrxb_immediate_t3;
- }
- if (op2 == 0) {
- int rm = opcode & 0xf;
-
- if (rt == 0x0f)
- sprintf(cp, "PLD\t");
- else
- sprintf(cp, "LDRB.W\tr%d, ", rt);
- immed = (opcode >> 4) & 0x3;
- cp = strchr(cp, 0);
- sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed);
- return ERROR_OK;
- }
- break;
- case 1:
- if ((rn & rt) == 0xf)
- goto pld_literal;
- if (rt == 0xf) {
- immed = opcode & 0xfff;
- goto preload_immediate;
- }
- if (rn == 0x0f)
- goto ldrb_literal;
- mnemonic = "LDRB.W";
- immed = opcode & 0xfff;
- goto ldrxb_immediate_t2;
- case 2:
- if ((rn & rt) == 0xf) {
- immed = opcode & 0xfff;
- address = thumb_alignpc4(address);
- if (opcode & (1 << 23))
- address += immed;
- else
- address -= immed;
- sprintf(cp, "PLI\t%#8.8" PRIx32, address);
- return ERROR_OK;
- }
- if (rn == 0xf && rt != 0xf) {
-ldrsb_literal:
- immed = opcode & 0xfff;
- address = thumb_alignpc4(address);
- if (opcode & (1 << 23))
- address += immed;
- else
- address -= immed;
- sprintf(cp, "LDRSB\t%#8.8" PRIx32, address);
- return ERROR_OK;
- }
- if (rn == 0xf)
- break;
- if ((op2 & 0x3c) == 0x38) {
- immed = opcode & 0xff;
- sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %#2.2x",
- rt, rn, immed, immed);
- return ERROR_OK;
- }
- if ((op2 & 0x3c) == 0x30) {
- if (rt == 0xf) {
- immed = opcode & 0xff;
- immed = -immed; /* pli */
- sprintf(cp, "PLI\t[r%d, #%d]\t; -%#2.2x",
- rn, immed, -immed);
- return ERROR_OK;
- }
- mnemonic = "LDRSB";
- goto ldrxb_immediate_t3;
- }
- if ((op2 & 0x24) == 0x24) {
- mnemonic = "LDRSB";
- goto ldrxb_immediate_t3;
- }
- if (op2 == 0) {
- int rm = opcode & 0xf;
-
- if (rt == 0x0f)
- sprintf(cp, "PLI\t");
- else
- sprintf(cp, "LDRSB.W\tr%d, ", rt);
- immed = (opcode >> 4) & 0x3;
- cp = strchr(cp, 0);
- sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed);
- return ERROR_OK;
- }
- break;
- case 3:
- if (rt == 0xf) {
- immed = opcode & 0xfff;
- sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3x",
- rn, immed, immed);
- return ERROR_OK;
- }
- if (rn == 0xf)
- goto ldrsb_literal;
- immed = opcode & 0xfff;
- mnemonic = "LDRSB";
- goto ldrxb_immediate_t2;
- }
-
- return ERROR_COMMAND_SYNTAX_ERROR;
-}
-
-static int t2ev_load_halfword(uint32_t opcode, uint32_t address,
- struct arm_instruction *instruction, char *cp)
-{
- int rn = (opcode >> 16) & 0xf;
- int rt = (opcode >> 12) & 0xf;
- int op2 = (opcode >> 6) & 0x3f;
- char *sign = "";
- unsigned immed;
-
- if (rt == 0xf) {
- sprintf(cp, "HINT (UNALLOCATED)");
- return ERROR_OK;
- }
-
- if (opcode & (1 << 24))
- sign = "S";
-
- if ((opcode & (1 << 23)) == 0) {
- if (rn == 0xf) {
-ldrh_literal:
- immed = opcode & 0xfff;
- address = thumb_alignpc4(address);
- if (opcode & (1 << 23))
- address += immed;
- else
- address -= immed;
- sprintf(cp, "LDR%sH\tr%d, %#8.8" PRIx32,
- sign, rt, address);
- return ERROR_OK;
- }
- if (op2 == 0) {
- int rm = opcode & 0xf;
-
- immed = (opcode >> 4) & 0x3;
- sprintf(cp, "LDR%sH.W\tr%d, [r%d, r%d, LSL #%d]",
- sign, rt, rn, rm, immed);
- return ERROR_OK;
- }
- if ((op2 & 0x3c) == 0x38) {
- immed = opcode & 0xff;
- sprintf(cp, "LDR%sHT\tr%d, [r%d, #%d]\t; %#2.2x",
- sign, rt, rn, immed, immed);
- return ERROR_OK;
- }
- if ((op2 & 0x3c) == 0x30 || (op2 & 0x24) == 0x24) {
- char *p1 = "", *p2 = "]";
-
- immed = opcode & 0xff;
- if (!(opcode & 0x200))
- immed = -immed;
-
- /* two indexed modes will write back rn */
- if (opcode & 0x100) {
- if (opcode & 0x400) /* pre-indexed */
- p2 = "]!";
- else { /* post-indexed */
- p1 = "]";
- p2 = "";
- }
- }
- sprintf(cp, "LDR%sH\tr%d, [r%d%s, #%d%s\t; %#8.8x",
- sign, rt, rn, p1, immed, p2, immed);
- return ERROR_OK;
- }
- } else {
- if (rn == 0xf)
- goto ldrh_literal;
-
- immed = opcode & 0xfff;
- sprintf(cp, "LDR%sH%s\tr%d, [r%d, #%d]\t; %#6.6x",
- sign, *sign ? "" : ".W",
- rt, rn, immed, immed);
- return ERROR_OK;
- }
-
- return ERROR_COMMAND_SYNTAX_ERROR;
-}
-
-/*
- * REVISIT for Thumb2 instructions, instruction->type and friends aren't
- * always set. That means eventual arm_simulate_step() support for Thumb2
- * will need work in this area.
- */
-int thumb2_opcode(struct target *target, uint32_t address, struct arm_instruction *instruction)
-{
- int retval;
- uint16_t op;
- uint32_t opcode;
- char *cp;
-
- /* clear low bit ... it's set on function pointers */
- address &= ~1;
-
- /* clear fields, to avoid confusion */
- memset(instruction, 0, sizeof(struct arm_instruction));
-
- /* read first halfword, see if this is the only one */
- retval = target_read_u16(target, address, &op);
- if (retval != ERROR_OK)
- return retval;
-
- switch (op & 0xf800) {
- case 0xf800:
- case 0xf000:
- case 0xe800:
- /* 32-bit instructions */
- instruction->instruction_size = 4;
- opcode = op << 16;
- retval = target_read_u16(target, address + 2, &op);
- if (retval != ERROR_OK)
- return retval;
- opcode |= op;
- instruction->opcode = opcode;
- break;
- default:
- /* 16-bit: Thumb1 + IT + CBZ/CBNZ + ... */
- return thumb_evaluate_opcode(op, address, instruction);
- }
-
- snprintf(instruction->text, 128,
- "0x%8.8" PRIx32 " 0x%8.8" PRIx32 "\t",
- address, opcode);
- cp = strchr(instruction->text, 0);
- retval = ERROR_FAIL;
-
- /* ARMv7-M: A5.3.1 Data processing (modified immediate) */
- if ((opcode & 0x1a008000) == 0x10000000)
- retval = t2ev_data_mod_immed(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.3 Data processing (plain binary immediate) */
- else if ((opcode & 0x1a008000) == 0x12000000)
- retval = t2ev_data_immed(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.4 Branches and miscellaneous control */
- else if ((opcode & 0x18008000) == 0x10008000)
- retval = t2ev_b_misc(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.5 Load/store multiple */
- else if ((opcode & 0x1e400000) == 0x08000000)
- retval = t2ev_ldm_stm(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch */
- else if ((opcode & 0x1e400000) == 0x08400000)
- retval = t2ev_ldrex_strex(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.7 Load word */
- else if ((opcode & 0x1f700000) == 0x18500000)
- retval = t2ev_load_word(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.8 Load halfword, unallocated memory hints */
- else if ((opcode & 0x1e700000) == 0x18300000)
- retval = t2ev_load_halfword(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.9 Load byte, memory hints */
- else if ((opcode & 0x1e700000) == 0x18100000)
- retval = t2ev_load_byte_hints(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.10 Store single data item */
- else if ((opcode & 0x1f100000) == 0x18000000)
- retval = t2ev_store_single(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.11 Data processing (shifted register) */
- else if ((opcode & 0x1e000000) == 0x0a000000)
- retval = t2ev_data_shift(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.12 Data processing (register)
- * and A5.3.13 Miscellaneous operations
- */
- else if ((opcode & 0x1f000000) == 0x1a000000)
- retval = t2ev_data_reg(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.14 Multiply, and multiply accumulate */
- else if ((opcode & 0x1f800000) == 0x1b000000)
- retval = t2ev_mul32(opcode, address, instruction, cp);
-
- /* ARMv7-M: A5.3.15 Long multiply, long multiply accumulate, divide */
- else if ((opcode & 0x1f800000) == 0x1b800000)
- retval = t2ev_mul64_div(opcode, address, instruction, cp);
-
- if (retval == ERROR_OK)
- return retval;
-
- /*
- * Thumb2 also supports coprocessor, ThumbEE, and DSP/Media (SIMD)
- * instructions; not yet handled here.
- */
-
- if (retval == ERROR_COMMAND_SYNTAX_ERROR) {
- instruction->type = ARM_UNDEFINED_INSTRUCTION;
- strcpy(cp, "UNDEFINED OPCODE");
- return ERROR_OK;
- }
-
- LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08" PRIx32 ")",
- opcode);
-
- strcpy(cp, "(32-bit Thumb2 ...)");
- return ERROR_OK;
-}
-
-int arm_access_size(struct arm_instruction *instruction)
-{
- if ((instruction->type == ARM_LDRB)
- || (instruction->type == ARM_LDRBT)
- || (instruction->type == ARM_LDRSB)
- || (instruction->type == ARM_STRB)
- || (instruction->type == ARM_STRBT))
- return 1;
- else if ((instruction->type == ARM_LDRH)
- || (instruction->type == ARM_LDRSH)
- || (instruction->type == ARM_STRH))
- return 2;
- else if ((instruction->type == ARM_LDR)
- || (instruction->type == ARM_LDRT)
- || (instruction->type == ARM_STR)
- || (instruction->type == ARM_STRT))
- return 4;
- else if ((instruction->type == ARM_LDRD)
- || (instruction->type == ARM_STRD))
- return 8;
- else {
- LOG_ERROR("BUG: instruction type %i isn't a load/store instruction",
- instruction->type);
- return 0;
- }
-}