+ if (dap->asize > 32) {
+ retval = dap_queue_dp_read(dap, DP_BASEPTR1, &baseptr_upper);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ retval = dap_dp_read_atomic(dap, DP_BASEPTR0, &baseptr_lower);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if ((baseptr_lower & DP_BASEPTR0_VALID) != DP_BASEPTR0_VALID) {
+ command_print(cmd, "System root table not present");
+ return ERROR_FAIL;
+ }
+
+ baseptr_lower &= ~0x0fff;
+ *baseptr = (((uint64_t)baseptr_upper) << 32) | baseptr_lower;
+
+ return ERROR_OK;
+}
+
+/**
+ * Method to access the CoreSight component.
+ * On ADIv5, CoreSight components are on the bus behind a MEM-AP.
+ * On ADIv6, CoreSight components can either be on the bus behind a MEM-AP
+ * or directly in the AP.
+ */
+enum coresight_access_mode {
+ CS_ACCESS_AP,
+ CS_ACCESS_MEM_AP,
+};
+
+/** Holds registers and coordinates of a CoreSight component */
+struct cs_component_vals {
+ struct adiv5_ap *ap;
+ target_addr_t component_base;
+ uint64_t pid;
+ uint32_t cid;
+ uint32_t devarch;
+ uint32_t devid;
+ uint32_t devtype_memtype;
+ enum coresight_access_mode mode;
+};
+
+/**
+ * Helper to read CoreSight component's registers, either on the bus
+ * behind a MEM-AP or directly in the AP.
+ *
+ * @param mode Method to access the component (AP or MEM-AP).
+ * @param ap Pointer to AP containing the component.
+ * @param component_base On MEM-AP access method, base address of the component.
+ * @param reg Offset of the component's register to read.
+ * @param value Pointer to the store the read value.
+ *
+ * @return ERROR_OK on success, else a fault code.
+ */
+static int dap_queue_read_reg(enum coresight_access_mode mode, struct adiv5_ap *ap,
+ uint64_t component_base, unsigned int reg, uint32_t *value)
+{
+ if (mode == CS_ACCESS_AP)
+ return dap_queue_ap_read(ap, reg, value);
+
+ /* mode == CS_ACCESS_MEM_AP */
+ return mem_ap_read_u32(ap, component_base + reg, value);
+}
+
+/**
+ * Read the CoreSight registers needed during ROM Table Parsing (RTP).
+ *
+ * @param mode Method to access the component (AP or MEM-AP).
+ * @param ap Pointer to AP containing the component.
+ * @param component_base On MEM-AP access method, base address of the component.
+ * @param v Pointer to the struct holding the value of registers.
+ *
+ * @return ERROR_OK on success, else a fault code.
+ */
+static int rtp_read_cs_regs(enum coresight_access_mode mode, struct adiv5_ap *ap,
+ target_addr_t component_base, struct cs_component_vals *v)
+{
+ assert(IS_ALIGNED(component_base, ARM_CS_ALIGN));
+ assert(ap && v);
+
+ uint32_t cid0, cid1, cid2, cid3;
+ uint32_t pid0, pid1, pid2, pid3, pid4;
+ int retval = ERROR_OK;
+
+ v->ap = ap;
+ v->component_base = component_base;
+ v->mode = mode;
+
+ /* sort by offset to gain speed */
+
+ /*
+ * Registers DEVARCH, DEVID and DEVTYPE are valid on Class 0x9 devices
+ * only, but are at offset above 0xf00, so can be read on any device
+ * without triggering error. Read them for eventual use on Class 0x9.
+ */
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVARCH, &v->devarch);
+
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVID, &v->devid);
+
+ /* Same address as ARM_CS_C1_MEMTYPE */
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVTYPE, &v->devtype_memtype);
+
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR4, &pid4);
+
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR0, &pid0);
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR1, &pid1);
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR2, &pid2);
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR3, &pid3);
+
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR0, &cid0);
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR1, &cid1);
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR2, &cid2);
+ if (retval == ERROR_OK)
+ retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR3, &cid3);
+
+ if (retval == ERROR_OK)
+ retval = dap_run(ap->dap);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("Failed read CoreSight registers");
+ return retval;
+ }
+
+ v->cid = (cid3 & 0xff) << 24
+ | (cid2 & 0xff) << 16
+ | (cid1 & 0xff) << 8
+ | (cid0 & 0xff);
+ v->pid = (uint64_t)(pid4 & 0xff) << 32
+ | (pid3 & 0xff) << 24
+ | (pid2 & 0xff) << 16
+ | (pid1 & 0xff) << 8
+ | (pid0 & 0xff);
+
+ return ERROR_OK;
+}
+
+/* Part number interpretations are from Cortex
+ * core specs, the CoreSight components TRM
+ * (ARM DDI 0314H), CoreSight System Design
+ * Guide (ARM DGI 0012D) and ETM specs; also
+ * from chip observation (e.g. TI SDTI).
+ */
+
+static const struct dap_part_nums {
+ uint16_t designer_id;
+ uint16_t part_num;
+ const char *type;
+ const char *full;
+} dap_part_nums[] = {
+ { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
+ { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
+ { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
+ { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
+ { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
+ { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
+ { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
+ { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
+ { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
+ { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
+ { ARM_ID, 0x193, "SoC-600 TSGEN", "(Timestamp Generator)", },
+ { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
+ { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
+ { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
+ { ARM_ID, 0x492, "Cortex-R52 GICD", "(Distributor)", },
+ { ARM_ID, 0x493, "Cortex-R52 GICR", "(Redistributor)", },
+ { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
+ { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
+ { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
+ { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4b8, "Cortex-R52 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
+ { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
+ { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
+ { ARM_ID, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", },
+ { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
+ { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
+ { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
+ { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
+ { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
+ { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
+ { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
+ { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
+ { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
+ { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
+ { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
+ { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
+ { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
+ { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
+ { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
+ { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
+ { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
+ { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
+ { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
+ { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9b6, "Cortex-R52 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
+ { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
+ { ARM_ID, 0x9e2, "SoC-600 APB-AP", "(APB4 Memory Access Port)", },
+ { ARM_ID, 0x9e3, "SoC-600 AHB-AP", "(AHB5 Memory Access Port)", },
+ { ARM_ID, 0x9e4, "SoC-600 AXI-AP", "(AXI Memory Access Port)", },
+ { ARM_ID, 0x9e5, "SoC-600 APv1 Adapter", "(Access Port v1 Adapter)", },
+ { ARM_ID, 0x9e6, "SoC-600 JTAG-AP", "(JTAG Access Port)", },
+ { ARM_ID, 0x9e7, "SoC-600 TPIU", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x9e8, "SoC-600 TMC ETR/ETS", "(Embedded Trace Router/Streamer)", },
+ { ARM_ID, 0x9e9, "SoC-600 TMC ETB", "(Embedded Trace Buffer)", },
+ { ARM_ID, 0x9ea, "SoC-600 TMC ETF", "(Embedded Trace FIFO)", },
+ { ARM_ID, 0x9eb, "SoC-600 ATB Funnel", "(Trace Funnel)", },
+ { ARM_ID, 0x9ec, "SoC-600 ATB Replicator", "(Trace Replicator)", },
+ { ARM_ID, 0x9ed, "SoC-600 CTI", "(Cross Trigger)", },
+ { ARM_ID, 0x9ee, "SoC-600 CATU", "(Address Translation Unit)", },
+ { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd0c, "Neoverse N1", "(Debug Unit)", },
+ { ARM_ID, 0xd13, "Cortex-R52 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd49, "Neoverse N2", "(Debug Unit)", },
+ { 0x017, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
+ { 0x017, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
+ { 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" },
+ { 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
+ { 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" },
+ { 0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
+ { 0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
+ { 0x065, 0x000, "SHARC+/Blackfin+", "", },
+ { 0x070, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
+ { 0x0bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
+ { 0x0bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
+ { 0x0bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
+ { 0x0bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
+ { 0x1eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
+ { 0x1eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
+ { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
+ { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", },
+ { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
+};
+
+static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
+{
+ static const struct dap_part_nums unknown = {
+ .type = "Unrecognized",
+ .full = "",
+ };
+
+ for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++)
+ if (dap_part_nums[i].designer_id == designer_id && dap_part_nums[i].part_num == part_num)
+ return &dap_part_nums[i];
+
+ return &unknown;
+}
+
+static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
+{
+ const char *major = "Reserved", *subtype = "Reserved";
+ const unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
+ const unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
+ switch (devtype_major) {
+ case 0:
+ major = "Miscellaneous";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 4:
+ subtype = "Validation component";
+ break;
+ }
+ break;
+ case 1:
+ major = "Trace Sink";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Port";
+ break;
+ case 2:
+ subtype = "Buffer";
+ break;
+ case 3:
+ subtype = "Router";
+ break;
+ }
+ break;
+ case 2:
+ major = "Trace Link";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Funnel, router";
+ break;
+ case 2:
+ subtype = "Filter";
+ break;
+ case 3:
+ subtype = "FIFO, buffer";
+ break;
+ }
+ break;
+ case 3:
+ major = "Trace Source";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Processor";
+ break;
+ case 2:
+ subtype = "DSP";
+ break;
+ case 3:
+ subtype = "Engine/Coprocessor";
+ break;
+ case 4:
+ subtype = "Bus";
+ break;
+ case 6:
+ subtype = "Software";
+ break;
+ }
+ break;
+ case 4:
+ major = "Debug Control";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Trigger Matrix";
+ break;
+ case 2:
+ subtype = "Debug Auth";
+ break;
+ case 3:
+ subtype = "Power Requestor";
+ break;
+ }
+ break;
+ case 5:
+ major = "Debug Logic";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Processor";
+ break;
+ case 2:
+ subtype = "DSP";
+ break;
+ case 3:
+ subtype = "Engine/Coprocessor";
+ break;
+ case 4:
+ subtype = "Bus";
+ break;
+ case 5:
+ subtype = "Memory";
+ break;
+ }
+ break;
+ case 6:
+ major = "Performance Monitor";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Processor";
+ break;
+ case 2:
+ subtype = "DSP";
+ break;
+ case 3:
+ subtype = "Engine/Coprocessor";
+ break;
+ case 4:
+ subtype = "Bus";
+ break;
+ case 5:
+ subtype = "Memory";
+ break;
+ }
+ break;
+ }
+ command_print(cmd, "\t\tType is 0x%02x, %s, %s",
+ devtype & ARM_CS_C9_DEVTYPE_MASK,
+ major, subtype);
+ return ERROR_OK;
+}
+
+/**
+ * Actions/operations to be executed while parsing ROM tables.
+ */
+struct rtp_ops {
+ /**
+ * Executed at the start of a new AP, typically to print the AP header.
+ * @param ap Pointer to AP.
+ * @param depth The current depth level of ROM table.
+ * @param priv Pointer to private data.
+ * @return ERROR_OK on success, else a fault code.
+ */
+ int (*ap_header)(struct adiv5_ap *ap, int depth, void *priv);
+ /**
+ * Executed at the start of a new MEM-AP, typically to print the MEM-AP header.
+ * @param retval Error encountered while reading AP.
+ * @param ap Pointer to AP.
+ * @param dbgbase Value of MEM-AP Debug Base Address register.
+ * @param apid Value of MEM-AP IDR Identification Register.
+ * @param depth The current depth level of ROM table.
+ * @param priv Pointer to private data.
+ * @return ERROR_OK on success, else a fault code.
+ */
+ int (*mem_ap_header)(int retval, struct adiv5_ap *ap, uint64_t dbgbase,
+ uint32_t apid, int depth, void *priv);
+ /**
+ * Executed when a CoreSight component is parsed, typically to print
+ * information on the component.
+ * @param retval Error encountered while reading component's registers.
+ * @param v Pointer to a container of the component's registers.
+ * @param depth The current depth level of ROM table.
+ * @param priv Pointer to private data.
+ * @return ERROR_OK on success, else a fault code.
+ */
+ int (*cs_component)(int retval, struct cs_component_vals *v, int depth, void *priv);
+ /**
+ * Executed for each entry of a ROM table, typically to print the entry
+ * and information about validity or end-of-table mark.
+ * @param retval Error encountered while reading the ROM table entry.
+ * @param depth The current depth level of ROM table.
+ * @param offset The offset of the entry in the ROM table.
+ * @param romentry The value of the ROM table entry.
+ * @param priv Pointer to private data.
+ * @return ERROR_OK on success, else a fault code.
+ */
+ int (*rom_table_entry)(int retval, int depth, unsigned int offset, uint64_t romentry,
+ void *priv);
+ /**
+ * Private data
+ */
+ void *priv;
+};
+
+/**
+ * Wrapper around struct rtp_ops::ap_header.
+ */
+static int rtp_ops_ap_header(const struct rtp_ops *ops,
+ struct adiv5_ap *ap, int depth)
+{
+ if (ops->ap_header)
+ return ops->ap_header(ap, depth, ops->priv);
+
+ return ERROR_OK;
+}