- if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
- command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
- ", CID2 0x%2.2" PRIx32
- ", CID1 0x%2.2" PRIx32
- ", CID0 0x%2.2" PRIx32,
- cid3, cid2, cid1, cid0);
- if (memtype & 0x01)
- command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
- else
- command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
- "Dedicated debug bus.");
-
- /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
- entry_offset = 0;
- do
- {
- mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
- command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
- if (romentry&0x01)
- {
- uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
- uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
- uint32_t component_start, component_base;
- unsigned part_num;
- char *type, *full;
-
- component_base = (uint32_t)((dbgbase & 0xFFFFF000)
- + (int)(romentry & 0xFFFFF000));
- mem_ap_read_atomic_u32(swjdp,
- (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
- mem_ap_read_atomic_u32(swjdp,
- (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
- mem_ap_read_atomic_u32(swjdp,
- (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
- mem_ap_read_atomic_u32(swjdp,
- (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
- mem_ap_read_atomic_u32(swjdp,
- (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
- mem_ap_read_atomic_u32(swjdp,
- (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
- mem_ap_read_atomic_u32(swjdp,
- (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
- mem_ap_read_atomic_u32(swjdp,
- (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
- mem_ap_read_atomic_u32(swjdp,
- (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
- component_start = component_base - 0x1000*(c_pid4 >> 4);
-
- command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
- ", start address 0x%" PRIx32,
- component_base, component_start);
- command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
- (int) (c_cid1 >> 4) & 0xf,
- /* See ARM IHI 0029B Table 3-3 */
- class_description[(c_cid1 >> 4) & 0xf]);
-
- /* CoreSight component? */
- if (((c_cid1 >> 4) & 0x0f) == 9) {
- uint32_t devtype;
- unsigned minor;
- char *major = "Reserved", *subtype = "Reserved";
-
- mem_ap_read_atomic_u32(swjdp,
- (component_base & 0xfffff000) | 0xfcc,
- &devtype);
- minor = (devtype >> 4) & 0x0f;
- switch (devtype & 0x0f) {
+ retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
+ if (retval != ERROR_OK)
+ return retval;
+ c_cid0 &= 0xff;
+ retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
+ if (retval != ERROR_OK)
+ return retval;
+ c_cid1 &= 0xff;
+ retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
+ if (retval != ERROR_OK)
+ return retval;
+ c_cid2 &= 0xff;
+ retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
+ if (retval != ERROR_OK)
+ return retval;
+ c_cid3 &= 0xff;
+
+ command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
+ "start address 0x%" PRIx32, component_base,
+ /* component may take multiple 4K pages */
+ (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
+ command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
+ (c_cid1 >> 4) & 0xf,
+ /* See ARM IHI 0029B Table 3-3 */
+ class_description[(c_cid1 >> 4) & 0xf]);
+
+ /* CoreSight component? */
+ if (((c_cid1 >> 4) & 0x0f) == 9) {
+ uint32_t devtype;
+ unsigned minor;
+ char *major = "Reserved", *subtype = "Reserved";
+
+ retval = mem_ap_read_atomic_u32(dap,
+ (component_base & 0xfffff000) | 0xfcc,
+ &devtype);
+ if (retval != ERROR_OK)
+ return retval;
+ minor = (devtype >> 4) & 0x0f;
+ switch (devtype & 0x0f) {
+ case 0:
+ major = "Miscellaneous";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 4:
+ subtype = "Validation component";
+ break;
+ }
+ break;
+ case 1:
+ major = "Trace Sink";
+ switch (minor) {