+ return target_register_timer_callback(arm7_9_handle_target_request,
+ 1, 1, target);
+}
+
+int arm7_9_register_commands(struct command_context_s *cmd_ctx)
+{
+ command_t *arm7_9_cmd;
+
+ arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9",
+ NULL, COMMAND_ANY, "arm7/9 specific commands");
+
+ register_command(cmd_ctx, arm7_9_cmd, "write_xpsr",
+ handle_arm7_9_write_xpsr_command, COMMAND_EXEC,
+ "write program status register <value> <not cpsr | spsr>");
+ register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8",
+ handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC,
+ "write program status register "
+ "<8bit immediate> <rotate> <not cpsr | spsr>");
+
+ register_command(cmd_ctx, arm7_9_cmd, "write_core_reg",
+ handle_arm7_9_write_core_reg_command, COMMAND_EXEC,
+ "write core register <num> <mode> <value>");
+
+ register_command(cmd_ctx, arm7_9_cmd, "dbgrq",
+ handle_arm7_9_dbgrq_command, COMMAND_ANY,
+ "use EmbeddedICE dbgrq instead of breakpoint "
+ "for target halt requests <enable | disable>");
+ register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access",
+ handle_arm7_9_fast_memory_access_command, COMMAND_ANY,
+ "use fast memory accesses instead of slower "
+ "but potentially safer accesses <enable | disable>");
+ register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads",
+ handle_arm7_9_dcc_downloads_command, COMMAND_ANY,
+ "use DCC downloads for larger memory writes <enable | disable>");
+
+ armv4_5_register_commands(cmd_ctx);
+
+ etm_register_commands(cmd_ctx);