- ARM11_DEBUG_V6 = 0x01,
- ARM11_DEBUG_V61 = 0x02,
- ARM11_DEBUG_V7 = 0x03,
- ARM11_DEBUG_V7_CP14 = 0x04,
-};
-
-typedef struct arm11_common_s
-{
- target_t * target; /**< Reference back to the owner */
-
- /** \name Processor type detection */
- /*@{*/
-
- uint32_t device_id; /**< IDCODE readout */
- uint32_t didr; /**< DIDR readout (debug capabilities) */
- uint8_t implementor; /**< DIDR Implementor readout */
-
- size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
- size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
-
- enum arm11_debug_version
- debug_version; /**< ARM debug architecture from DIDR */
- /*@}*/
-
- uint32_t last_dscr; /**< Last retrieved DSCR value;
- Use only for debug message generation */
-
- bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
-
- /** \name Shadow registers to save processor state */
- /*@{*/
-
- reg_t * reg_list; /**< target register list */
- uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
-
- /*@}*/
-
- struct arm11_register_history
- reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
-
- size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
- size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
-
- // GA
- reg_cache_t *core_cache;
-} arm11_common_t;
-