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Transform 'u32' to 'uint32_t' in src/target/arm*
[fw/openocd]
/
src
/
target
/
arm11.c
diff --git
a/src/target/arm11.c
b/src/target/arm11.c
index 68da3f668e8e4f191f9ff3d08e2afcfe6894493d..765846e2c3a96e6efec5be43ecc7758f1983c8b1 100644
(file)
--- a/
src/target/arm11.c
+++ b/
src/target/arm11.c
@@
-1,5
+1,6
@@
/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
+ * Michael Bruck *
* *
* Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
* *
* *
* Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
* *
@@
-26,11
+27,8
@@
#endif
#include "arm11.h"
#endif
#include "arm11.h"
-#include "jtag.h"
-#include "log.h"
+#include "target_type.h"
-#include <stdlib.h>
-#include <string.h>
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
@@
-52,7
+50,7
@@
static int arm11_on_enter_debug_state(arm11_common_t * arm11);
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
-u
32
arm11_vcr = 0;
+u
int32_t
arm11_vcr = 0;
bool arm11_config_memrw_no_increment = false;
bool arm11_config_step_irq_enable = false;
bool arm11_config_memrw_no_increment = false;
bool arm11_config_step_irq_enable = false;
@@
-134,7
+132,7
@@
enum arm11_regtype
typedef struct arm11_reg_defs_s
{
char * name;
typedef struct arm11_reg_defs_s
{
char * name;
- u
32
num;
+ u
int32_t
num;
int gdb_num;
enum arm11_regtype type;
} arm11_reg_defs_t;
int gdb_num;
enum arm11_regtype type;
} arm11_reg_defs_t;
@@
-290,14
+288,14
@@
enum arm11_regcache_ids
#define ARM11_GDB_REGISTER_COUNT 26
#define ARM11_GDB_REGISTER_COUNT 26
-u
8
arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+u
int8_t
arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
reg_t arm11_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
reg_t arm11_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
-u
8
arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+u
int8_t
arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
reg_t arm11_gdb_dummy_fps_reg =
{
reg_t arm11_gdb_dummy_fps_reg =
{
@@
-313,11
+311,11
@@
reg_t arm11_gdb_dummy_fps_reg =
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
-int arm11_check_init(arm11_common_t * arm11, u
32
* dscr)
+int arm11_check_init(arm11_common_t * arm11, u
int32_t
* dscr)
{
FNC_INFO;
{
FNC_INFO;
- u
32
dscr_local_tmp_copy;
+ u
int32_t
dscr_local_tmp_copy;
if (!dscr)
{
if (!dscr)
{
@@
-340,7
+338,9
@@
int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
if (*dscr & ARM11_DSCR_CORE_HALTED)
{
/** \todo TODO: this needs further scrutiny because
if (*dscr & ARM11_DSCR_CORE_HALTED)
{
/** \todo TODO: this needs further scrutiny because
- * arm11_on_enter_debug_state() never gets properly called
+ * arm11_on_enter_debug_state() never gets properly called.
+ * As a result we don't read the actual register states from
+ * the target.
*/
arm11->target->state = TARGET_HALTED;
*/
arm11->target->state = TARGET_HALTED;
@@
-393,8
+393,8
@@
static int arm11_on_enter_debug_state(arm11_common_t * arm11)
scan_field_t chain5_fields[3];
arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
scan_field_t chain5_fields[3];
arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
- arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
- arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
+ arm11_setup_field(arm11, 1, NULL, NULL,
chain5_fields + 1);
+ arm11_setup_field(arm11, 1, NULL, NULL,
chain5_fields + 2);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
@@
-408,7
+408,7
@@
static int arm11_on_enter_debug_state(arm11_common_t * arm11)
/* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
ARM1136 seems to require this to issue ITR's as well */
/* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
ARM1136 seems to require this to issue ITR's as well */
- u
32
new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
+ u
int32_t
new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
/* this executes JTAG queue: */
/* this executes JTAG queue: */
@@
-430,7
+430,7
@@
static int arm11_on_enter_debug_state(arm11_common_t * arm11)
/* mcr 15, 0, r0, cr7, cr10, {4} */
arm11_run_instr_no_data1(arm11, 0xee070f9a);
/* mcr 15, 0, r0, cr7, cr10, {4} */
arm11_run_instr_no_data1(arm11, 0xee070f9a);
- u
32
dscr = arm11_read_DSCR(arm11);
+ u
int32_t
dscr = arm11_read_DSCR(arm11);
LOG_DEBUG("DRAIN, DSCR %08x", dscr);
LOG_DEBUG("DRAIN, DSCR %08x", dscr);
@@
-579,7
+579,7
@@
int arm11_leave_debug_state(arm11_common_t * arm11)
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
- u
32
DSCR;
+ u
int32_t
DSCR;
CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
@@
-630,8
+630,8
@@
int arm11_leave_debug_state(arm11_common_t * arm11)
scan_field_t chain5_fields[3];
scan_field_t chain5_fields[3];
- u
8
Ready = 0; /* ignored */
- u
8
Valid = 0; /* ignored */
+ u
int8_t
Ready = 0; /* ignored */
+ u
int8_t
Valid = 0; /* ignored */
arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
@@
-668,7
+668,7
@@
int arm11_poll(struct target_s *target)
if (arm11->trst_active)
return ERROR_OK;
if (arm11->trst_active)
return ERROR_OK;
- u
32
dscr;
+ u
int32_t
dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
@@
-683,7
+683,7
@@
int arm11_poll(struct target_s *target)
enum target_state old_state = target->state;
LOG_DEBUG("enter TARGET_HALTED");
enum target_state old_state = target->state;
LOG_DEBUG("enter TARGET_HALTED");
- target->state = TARGET_HALTED;
+ target->state
= TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
arm11_on_enter_debug_state(arm11);
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
arm11_on_enter_debug_state(arm11);
@@
-696,7
+696,7
@@
int arm11_poll(struct target_s *target)
if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
{
LOG_DEBUG("enter TARGET_RUNNING");
if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
{
LOG_DEBUG("enter TARGET_RUNNING");
- target->state = TARGET_RUNNING;
+ target->state
= TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
}
}
target->debug_reason = DBG_REASON_NOTHALTED;
}
}
@@
-717,7
+717,7
@@
int arm11_arch_state(struct target_s *target)
}
/* target request support */
}
/* target request support */
-int arm11_target_request_data(struct target_s *target, u
32 size, u8
*buffer)
+int arm11_target_request_data(struct target_s *target, u
int32_t size, uint8_t
*buffer)
{
FNC_INFO_NOTIMPLEMENTED;
{
FNC_INFO_NOTIMPLEMENTED;
@@
-755,7
+755,7
@@
int arm11_halt(struct target_s *target)
CHECK_RETVAL(jtag_execute_queue());
CHECK_RETVAL(jtag_execute_queue());
- u
32
dscr;
+ u
int32_t
dscr;
while (1)
{
while (1)
{
@@
-779,7
+779,7
@@
int arm11_halt(struct target_s *target)
return ERROR_OK;
}
return ERROR_OK;
}
-int arm11_resume(struct target_s *target, int current, u
32
address, int handle_breakpoints, int debug_execution)
+int arm11_resume(struct target_s *target, int current, u
int32_t
address, int handle_breakpoints, int debug_execution)
{
FNC_INFO;
{
FNC_INFO;
@@
-856,7
+856,7
@@
int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
while (1)
{
while (1)
{
- u
32
dscr;
+ u
int32_t
dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
@@
-884,7
+884,7
@@
int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
return ERROR_OK;
}
return ERROR_OK;
}
-int arm11_step(struct target_s *target, int current, u
32
address, int handle_breakpoints)
+int arm11_step(struct target_s *target, int current, u
int32_t
address, int handle_breakpoints)
{
FNC_INFO;
{
FNC_INFO;
@@
-906,7
+906,7
@@
int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
/** \todo TODO: Thumb not supported here */
/** \todo TODO: Thumb not supported here */
- u
32
next_instruction;
+ u
int32_t
next_instruction;
CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
@@
-975,7
+975,7
@@
int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
while (1)
{
while (1)
{
- u
32
dscr;
+ u
int32_t
dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
@@
-1090,9
+1090,9
@@
int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
-int arm11_read_memory(struct target_s *target, u
32 address, u32 size, u32 count, u8
*buffer)
+int arm11_read_memory(struct target_s *target, u
int32_t address, uint32_t size, uint32_t count, uint8_t
*buffer)
{
{
- /** \todo TODO: check if buffer cast to u
32* and u16
* might cause alignment problems */
+ /** \todo TODO: check if buffer cast to u
int32_t* and uint16_t
* might cause alignment problems */
FNC_INFO;
FNC_INFO;
@@
-1124,7
+1124,7
@@
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
- u
32
res;
+ u
int32_t
res;
/* MCR p14,0,R1,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
/* MCR p14,0,R1,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
@@
-1143,13
+1143,13
@@
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
- u
32
res;
+ u
int32_t
res;
/* MCR p14,0,R1,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
/* MCR p14,0,R1,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
- u
16
svalue = res;
- memcpy(buffer + count * sizeof(u
16), &svalue, sizeof(u16
));
+ u
int16_t
svalue = res;
+ memcpy(buffer + count * sizeof(u
int16_t), &svalue, sizeof(uint16_t
));
}
break;
}
break;
@@
-1157,9
+1157,9
@@
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
case 4:
{
case 4:
{
- u
32
instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
- /** \todo TODO: buffer cast to u
32
* causes alignment warnings */
- u
32 *words = (u32
*)buffer;
+ u
int32_t
instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
+ /** \todo TODO: buffer cast to u
int32_t
* causes alignment warnings */
+ u
int32_t *words = (uint32_t
*)buffer;
/* LDC p14,c5,[R0],#4 */
/* LDC p14,c5,[R0] */
/* LDC p14,c5,[R0],#4 */
/* LDC p14,c5,[R0] */
@@
-1173,7
+1173,7
@@
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
return ERROR_OK;
}
return ERROR_OK;
}
-int arm11_write_memory(struct target_s *target, u
32 address, u32 size, u32 count, u8
*buffer)
+int arm11_write_memory(struct target_s *target, u
int32_t address, uint32_t size, uint32_t count, uint8_t
*buffer)
{
FNC_INFO;
{
FNC_INFO;
@@
-1218,8
+1218,8
@@
int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
for (size_t i = 0; i < count; i++)
{
for (size_t i = 0; i < count; i++)
{
- u
16
value;
- memcpy(&value, buffer + count * sizeof(u
16), sizeof(u16
));
+ u
int16_t
value;
+ memcpy(&value, buffer + count * sizeof(u
int16_t), sizeof(uint16_t
));
/* MRC p14,0,r1,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
/* MRC p14,0,r1,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
@@
-1234,10
+1234,10
@@
int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
}
case 4: {
}
case 4: {
- u
32
instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
+ u
int32_t
instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
- /** \todo TODO: buffer cast to u
32
* causes alignment warnings */
- u
32 *words = (u32
*)buffer;
+ /** \todo TODO: buffer cast to u
int32_t
* causes alignment warnings */
+ u
int32_t *words = (uint32_t
*)buffer;
if (!arm11_config_memwrite_burst)
{
if (!arm11_config_memwrite_burst)
{
@@
-1260,7
+1260,7
@@
int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
/* r0 verification */
if (!arm11_config_memrw_no_increment)
{
/* r0 verification */
if (!arm11_config_memrw_no_increment)
{
- u
32
r0;
+ u
int32_t
r0;
/* MCR p14,0,R0,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
/* MCR p14,0,R0,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
@@
-1285,7
+1285,7
@@
int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-int arm11_bulk_write_memory(struct target_s *target, u
32 address, u32 count, u8
*buffer)
+int arm11_bulk_write_memory(struct target_s *target, u
int32_t address, uint32_t count, uint8_t
*buffer)
{
FNC_INFO;
{
FNC_INFO;
@@
-1302,7
+1302,7
@@
int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8
* fallback code will read data from the target and calculate the CRC on the
* host.
*/
* fallback code will read data from the target and calculate the CRC on the
* host.
*/
-int arm11_checksum_memory(struct target_s *target, u
32 address, u32 count, u32
* checksum)
+int arm11_checksum_memory(struct target_s *target, u
int32_t address, uint32_t count, uint32_t
* checksum)
{
return ERROR_FAIL;
}
{
return ERROR_FAIL;
}
@@
-1369,24
+1369,18
@@
int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
// HACKHACKHACK - FIXME mode/state
/* target algorithm support */
int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
// HACKHACKHACK - FIXME mode/state
/* target algorithm support */
int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
- int num_reg_params, reg_param_t *reg_params, u
32 entry_point, u32
exit_point,
+ int num_reg_params, reg_param_t *reg_params, u
int32_t entry_point, uint32_t
exit_point,
int timeout_ms, void *arch_info)
{
arm11_common_t *arm11 = target->arch_info;
int timeout_ms, void *arch_info)
{
arm11_common_t *arm11 = target->arch_info;
- armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
// enum armv4_5_state core_state = arm11->core_state;
// enum armv4_5_mode core_mode = arm11->core_mode;
// enum armv4_5_state core_state = arm11->core_state;
// enum armv4_5_mode core_mode = arm11->core_mode;
- u
32
context[16];
- u
32
cpsr;
+ u
int32_t
context[16];
+ u
int32_t
cpsr;
int exit_breakpoint_size = 0;
int retval = ERROR_OK;
LOG_DEBUG("Running algorithm");
int exit_breakpoint_size = 0;
int retval = ERROR_OK;
LOG_DEBUG("Running algorithm");
- if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
- {
- LOG_ERROR("current target isn't an ARMV4/5 target");
- return ERROR_TARGET_INVALID;
- }
if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED)
{
@@
-1401,11
+1395,11
@@
int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
// Save regs
for (size_t i = 0; i < 16; i++)
{
// Save regs
for (size_t i = 0; i < 16; i++)
{
- context[i] = buf_get_u32((u
8
*)(&arm11->reg_values[i]),0,32);
- LOG_DEBUG("Save %i: 0x%x",i,context[i]);
+ context[i] = buf_get_u32((u
int8_t
*)(&arm11->reg_values[i]),0,32);
+ LOG_DEBUG("Save %
z
i: 0x%x",i,context[i]);
}
}
- cpsr = buf_get_u32((u
8
*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
+ cpsr = buf_get_u32((u
int8_t
*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
LOG_DEBUG("Save CPSR: 0x%x", cpsr);
for (int i = 0; i < num_mem_params; i++)
LOG_DEBUG("Save CPSR: 0x%x", cpsr);
for (int i = 0; i < num_mem_params; i++)
@@
-1445,6
+1439,12
@@
int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
exit(-1);
}
*/
exit(-1);
}
*/
+
+
+/* arm11 at this point only supports ARM not THUMB mode
+ however if this test needs to be reactivated the current state can be read back
+ from CPSR */
+#if 0
if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
{
LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
{
LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
@@
-1452,6
+1452,7
@@
int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
arm11->reg_list[ARM11_RC_CPSR].valid = 1;
}
arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
arm11->reg_list[ARM11_RC_CPSR].valid = 1;
}
+#endif
if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
{
if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
{
@@
-1520,10
+1521,10
@@
restore:
{
LOG_DEBUG("restoring register %s with value 0x%8.8x",
arm11->reg_list[i].name, context[i]);
{
LOG_DEBUG("restoring register %s with value 0x%8.8x",
arm11->reg_list[i].name, context[i]);
- arm11_set_reg(&arm11->reg_list[i], (u
8
*)&context[i]);
+ arm11_set_reg(&arm11->reg_list[i], (u
int8_t
*)&context[i]);
}
LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
}
LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
- arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u
8
*)&cpsr);
+ arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u
int8_t
*)&cpsr);
// arm11->core_state = core_state;
// arm11->core_mode = core_mode;
// arm11->core_state = core_state;
// arm11->core_mode = core_mode;
@@
-1539,12
+1540,6
@@
int arm11_target_create(struct target_s *target, Jim_Interp *interp)
arm11->target = target;
arm11->target = target;
- /* prepare JTAG information for the new target */
- arm11->jtag_info.tap = target->tap;
- arm11->jtag_info.scann_size = 5;
-
- CHECK_RETVAL(arm_jtag_setup_connection(&arm11->jtag_info));
-
if (target->tap==NULL)
return ERROR_FAIL;
if (target->tap==NULL)
return ERROR_FAIL;
@@
-1637,7
+1632,7
@@
int arm11_examine(struct target_s *target)
arm11_check_init(arm11, NULL);
arm11_check_init(arm11, NULL);
- target
->type->examined = 1
;
+ target
_set_examined(target)
;
return ERROR_OK;
}
return ERROR_OK;
}
@@
-1673,7
+1668,7
@@
int arm11_get_reg(reg_t *reg)
}
/** Change a value in the register cache */
}
/** Change a value in the register cache */
-int arm11_set_reg(reg_t *reg, u
8
*buf)
+int arm11_set_reg(reg_t *reg, u
int8_t
*buf)
{
FNC_INFO;
{
FNC_INFO;
@@
-1735,7
+1730,7
@@
int arm11_build_reg_cache(target_t *target)
r->name = rd->name;
r->size = 32;
r->name = rd->name;
r->size = 32;
- r->value = (u
8
*)(arm11->reg_values + i);
+ r->value = (u
int8_t
*)(arm11->reg_values + i);
r->dirty = 0;
r->valid = 0;
r->bitfield_desc = NULL;
r->dirty = 0;
r->valid = 0;
r->bitfield_desc = NULL;
@@
-1824,7
+1819,7
@@
int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args,
return ERROR_OK;
}
return ERROR_OK;
}
-const u
32
arm11_coproc_instruction_limits[] =
+const u
int32_t
arm11_coproc_instruction_limits[] =
{
15, /* coprocessor */
7, /* opcode 1 */
{
15, /* coprocessor */
7, /* opcode 1 */
@@
-1842,7
+1837,7
@@
arm11_common_t * arm11_find_target(const char * arg)
jtag_tap_t * tap;
target_t * t;
jtag_tap_t * tap;
target_t * t;
- tap = jtag_
TapByS
tring(arg);
+ tap = jtag_
tap_by_s
tring(arg);
if (!tap)
return 0;
if (!tap)
return 0;
@@
-1853,7
+1848,7
@@
arm11_common_t * arm11_find_target(const char * arg)
continue;
/* if (t->type == arm11_target) */
continue;
/* if (t->type == arm11_target) */
- if (0 == strcmp(t
->type->name
, "arm11"))
+ if (0 == strcmp(t
arget_get_name(t)
, "arm11"))
return t->arch_info;
}
return t->arch_info;
}
@@
-1884,7
+1879,7
@@
int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
return ERROR_TARGET_NOT_HALTED;
}
return ERROR_TARGET_NOT_HALTED;
}
- u
32
values[6];
+ u
int32_t
values[6];
for (size_t i = 0; i < (read ? 5 : 6); i++)
{
for (size_t i = 0; i < (read ? 5 : 6); i++)
{
@@
-1899,7
+1894,7
@@
int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
}
}
}
}
- u
32 instr = 0xEE000010
|
+ u
int32_t instr = 0xEE000010
|
(values[0] << 8) |
(values[1] << 21) |
(values[2] << 16) |
(values[0] << 8) |
(values[1] << 21) |
(values[2] << 16) |
@@
-1913,7
+1908,7
@@
int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
if (read)
{
if (read)
{
- u
32
result;
+ u
int32_t
result;
arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
@@
-1960,7
+1955,7
@@
int arm11_register_commands(struct command_context_s *cmd_ctx)
RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
memwrite_error_fatal)
RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
memwrite_error_fatal)
- )
+ )
/* memwrite */
RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
@@
-1976,7
+1971,7
@@
int arm11_register_commands(struct command_context_s *cmd_ctx)
RC_FINAL( "mcr", "Write Coprocessor register",
arm11_handle_mcr)
RC_FINAL( "mcr", "Write Coprocessor register",
arm11_handle_mcr)
- )
+ )
/* arm11 */
return ERROR_OK;
}
return ERROR_OK;
}