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armv7a: read ttbcr and ttb0/1 at every entry in debug state
[fw/openocd]
/
src
/
target
/
Makefile.am
diff --git
a/src/target/Makefile.am
b/src/target/Makefile.am
index d2aab0a5e3590d78170dc75c5f425f8b6b6c762e..fcc23adbe506946a930dd8349cd72b6dba624e91 100644
(file)
--- a/
src/target/Makefile.am
+++ b/
src/target/Makefile.am
@@
-39,6
+39,7
@@
TARGET_CORE_SRC = \
%D%/target.c \
%D%/target_request.c \
%D%/testee.c \
%D%/target.c \
%D%/target_request.c \
%D%/testee.c \
+ %D%/semihosting_common.c \
%D%/smp.c
ARMV4_5_SRC = \
%D%/smp.c
ARMV4_5_SRC = \
@@
-88,6
+89,7
@@
ARM_DEBUG_SRC = \
%D%/arm_simulator.c \
%D%/arm_semihosting.c \
%D%/arm_adi_v5.c \
%D%/arm_simulator.c \
%D%/arm_semihosting.c \
%D%/arm_adi_v5.c \
+ %D%/arm_dap.c \
%D%/armv7a_cache.c \
%D%/armv7a_cache_l2x.c \
%D%/adi_v5_jtag.c \
%D%/armv7a_cache.c \
%D%/armv7a_cache_l2x.c \
%D%/adi_v5_jtag.c \
@@
-209,6
+211,7
@@
INTEL_IA32_SRC = \
%D%/nds32_v3.h \
%D%/nds32_v3m.h \
%D%/nds32_aice.h \
%D%/nds32_v3.h \
%D%/nds32_v3m.h \
%D%/nds32_aice.h \
+ %D%/semihosting_common.h \
%D%/stm8.h \
%D%/lakemont.h \
%D%/x86_32_common.h \
%D%/stm8.h \
%D%/lakemont.h \
%D%/x86_32_common.h \