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adi_v5: use macro DP_APSEL_MAX to allocate struct adiv5_ap
[fw/openocd]
/
src
/
target
/
Makefile.am
diff --git
a/src/target/Makefile.am
b/src/target/Makefile.am
index 0021f44d543802231d38eb03f56d33e222c02948..42d809d0196fcabca14bdcdf30fb655bc06fc2b5 100644
(file)
--- a/
src/target/Makefile.am
+++ b/
src/target/Makefile.am
@@
-4,7
+4,9
@@
else
OOCD_TRACE_FILES =
endif
OOCD_TRACE_FILES =
endif
-%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
+%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
+ %D%/riscv/libriscv.la
+
STARTUP_TCL_SRCS += %D%/startup.tcl
STARTUP_TCL_SRCS += %D%/startup.tcl
@@
-19,16
+21,17
@@
noinst_LTLIBRARIES += %D%/libtarget.la
$(AVR32_SRC) \
$(MIPS32_SRC) \
$(NDS32_SRC) \
$(AVR32_SRC) \
$(MIPS32_SRC) \
$(NDS32_SRC) \
+ $(STM8_SRC) \
$(INTEL_IA32_SRC) \
$(INTEL_IA32_SRC) \
+ $(ESIRISC_SRC) \
+ $(ARC_SRC) \
%D%/avrt.c \
%D%/dsp563xx.c \
%D%/dsp563xx_once.c \
%D%/dsp5680xx.c \
%D%/avrt.c \
%D%/dsp563xx.c \
%D%/dsp563xx_once.c \
%D%/dsp5680xx.c \
- %D%/hla_target.c
-
-if TARGET64
-%C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
-endif
+ %D%/hla_target.c \
+ $(ARMV8_SRC) \
+ $(MIPS64_SRC)
TARGET_CORE_SRC = \
%D%/algorithm.c \
TARGET_CORE_SRC = \
%D%/algorithm.c \
@@
-38,6
+41,7
@@
TARGET_CORE_SRC = \
%D%/target.c \
%D%/target_request.c \
%D%/testee.c \
%D%/target.c \
%D%/target_request.c \
%D%/testee.c \
+ %D%/semihosting_common.c \
%D%/smp.c
ARMV4_5_SRC = \
%D%/smp.c
ARMV4_5_SRC = \
@@
-70,11
+74,14
@@
ARMV7_SRC = \
%D%/armv7m_trace.c \
%D%/cortex_m.c \
%D%/armv7a.c \
%D%/armv7m_trace.c \
%D%/cortex_m.c \
%D%/armv7a.c \
+ %D%/armv7a_mmu.c \
%D%/cortex_a.c \
%D%/cortex_a.c \
- %D%/ls1_sap.c
+ %D%/ls1_sap.c \
+ %D%/mem_ap.c
ARMV8_SRC = \
%D%/armv8_dpm.c \
ARMV8_SRC = \
%D%/armv8_dpm.c \
+ %D%/armv8_opcodes.c \
%D%/aarch64.c \
%D%/armv8.c \
%D%/armv8_cache.c
%D%/aarch64.c \
%D%/armv8.c \
%D%/armv8_cache.c
@@
-86,8
+93,10
@@
ARM_DEBUG_SRC = \
%D%/arm_simulator.c \
%D%/arm_semihosting.c \
%D%/arm_adi_v5.c \
%D%/arm_simulator.c \
%D%/arm_semihosting.c \
%D%/arm_adi_v5.c \
+ %D%/arm_dap.c \
%D%/armv7a_cache.c \
%D%/armv7a_cache_l2x.c \
%D%/armv7a_cache.c \
%D%/armv7a_cache_l2x.c \
+ %D%/adi_v5_dapdirect.c \
%D%/adi_v5_jtag.c \
%D%/adi_v5_swd.c \
%D%/embeddedice.c \
%D%/adi_v5_jtag.c \
%D%/adi_v5_swd.c \
%D%/embeddedice.c \
@@
-95,7
+104,8
@@
ARM_DEBUG_SRC = \
%D%/etb.c \
%D%/etm.c \
$(OOCD_TRACE_FILES) \
%D%/etb.c \
%D%/etm.c \
$(OOCD_TRACE_FILES) \
- %D%/etm_dummy.c
+ %D%/etm_dummy.c \
+ %D%/arm_cti.c
AVR32_SRC = \
%D%/avr32_ap7k.c \
AVR32_SRC = \
%D%/avr32_ap7k.c \
@@
-110,6
+120,14
@@
MIPS32_SRC = \
%D%/mips32_dmaacc.c \
%D%/mips_ejtag.c
%D%/mips32_dmaacc.c \
%D%/mips_ejtag.c
+MIPS64_SRC = \
+ %D%/mips64.c \
+ %D%/mips32_pracc.c \
+ %D%/mips64_pracc.c \
+ %D%/mips_mips64.c \
+ %D%/trace.c \
+ %D%/mips_ejtag.c
+
NDS32_SRC = \
%D%/nds32.c \
%D%/nds32_reg.c \
NDS32_SRC = \
%D%/nds32.c \
%D%/nds32_reg.c \
@@
-122,12
+140,26
@@
NDS32_SRC = \
%D%/nds32_v3m.c \
%D%/nds32_aice.c
%D%/nds32_v3m.c \
%D%/nds32_aice.c
+STM8_SRC = \
+ %D%/stm8.c
+
INTEL_IA32_SRC = \
%D%/quark_x10xx.c \
%D%/quark_d20xx.c \
%D%/lakemont.c \
%D%/x86_32_common.c
INTEL_IA32_SRC = \
%D%/quark_x10xx.c \
%D%/quark_d20xx.c \
%D%/lakemont.c \
%D%/x86_32_common.c
+ESIRISC_SRC = \
+ %D%/esirisc.c \
+ %D%/esirisc_jtag.c \
+ %D%/esirisc_trace.c
+
+ARC_SRC = \
+ %D%/arc.c \
+ %D%/arc_cmd.c \
+ %D%/arc_jtag.c \
+ %D%/arc_mem.c
+
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
%D%/arm.h \
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
%D%/arm.h \
@@
-136,6
+168,7
@@
INTEL_IA32_SRC = \
%D%/arm_adi_v5.h \
%D%/armv7a_cache.h \
%D%/armv7a_cache_l2x.h \
%D%/arm_adi_v5.h \
%D%/armv7a_cache.h \
%D%/armv7a_cache_l2x.h \
+ %D%/armv7a_mmu.h \
%D%/arm_disassembler.h \
%D%/arm_opcodes.h \
%D%/arm_simulator.h \
%D%/arm_disassembler.h \
%D%/arm_opcodes.h \
%D%/arm_simulator.h \
@@
-174,10
+207,13
@@
INTEL_IA32_SRC = \
%D%/etm_dummy.h \
%D%/image.h \
%D%/mips32.h \
%D%/etm_dummy.h \
%D%/image.h \
%D%/mips32.h \
+ %D%/mips64.h \
%D%/mips_m4k.h \
%D%/mips_m4k.h \
+ %D%/mips_mips64.h \
%D%/mips_ejtag.h \
%D%/mips32_pracc.h \
%D%/mips32_dmaacc.h \
%D%/mips_ejtag.h \
%D%/mips32_pracc.h \
%D%/mips32_dmaacc.h \
+ %D%/mips64_pracc.h \
%D%/oocd_trace.h \
%D%/register.h \
%D%/target.h \
%D%/oocd_trace.h \
%D%/register.h \
%D%/target.h \
@@
-203,7
+239,19
@@
INTEL_IA32_SRC = \
%D%/nds32_v3.h \
%D%/nds32_v3m.h \
%D%/nds32_aice.h \
%D%/nds32_v3.h \
%D%/nds32_v3m.h \
%D%/nds32_aice.h \
+ %D%/semihosting_common.h \
+ %D%/stm8.h \
%D%/lakemont.h \
%D%/lakemont.h \
- %D%/x86_32_common.h
+ %D%/x86_32_common.h \
+ %D%/arm_cti.h \
+ %D%/esirisc.h \
+ %D%/esirisc_jtag.h \
+ %D%/esirisc_regs.h \
+ %D%/esirisc_trace.h \
+ %D%/arc.h \
+ %D%/arc_cmd.h \
+ %D%/arc_jtag.h \
+ %D%/arc_mem.h
include %D%/openrisc/Makefile.am
include %D%/openrisc/Makefile.am
+include %D%/riscv/Makefile.am