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target/arm_adi_v5: fix sync CSW cache on apreg write
[fw/openocd]
/
src
/
target
/
Makefile.am
diff --git
a/src/target/Makefile.am
b/src/target/Makefile.am
index b1119e7df0e5fbe3bc2a6d9eb2ce6c7cb4ab2326..05f174870015938ee355d0c94ccf83c1f2d20c87 100644
(file)
--- a/
src/target/Makefile.am
+++ b/
src/target/Makefile.am
@@
-23,6
+23,7
@@
noinst_LTLIBRARIES += %D%/libtarget.la
$(NDS32_SRC) \
$(STM8_SRC) \
$(INTEL_IA32_SRC) \
$(NDS32_SRC) \
$(STM8_SRC) \
$(INTEL_IA32_SRC) \
+ $(ESIRISC_SRC) \
%D%/avrt.c \
%D%/dsp563xx.c \
%D%/dsp563xx_once.c \
%D%/avrt.c \
%D%/dsp563xx.c \
%D%/dsp563xx_once.c \
@@
-75,7
+76,8
@@
ARMV7_SRC = \
%D%/cortex_m.c \
%D%/armv7a.c \
%D%/cortex_a.c \
%D%/cortex_m.c \
%D%/armv7a.c \
%D%/cortex_a.c \
- %D%/ls1_sap.c
+ %D%/ls1_sap.c \
+ %D%/mem_ap.c
ARMV8_SRC = \
%D%/armv8_dpm.c \
ARMV8_SRC = \
%D%/armv8_dpm.c \
@@
-138,6
+140,10
@@
INTEL_IA32_SRC = \
%D%/lakemont.c \
%D%/x86_32_common.c
%D%/lakemont.c \
%D%/x86_32_common.c
+ESIRISC_SRC = \
+ %D%/esirisc.c \
+ %D%/esirisc_jtag.c
+
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
%D%/arm.h \
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
%D%/arm.h \
@@
-217,7
+223,10
@@
INTEL_IA32_SRC = \
%D%/stm8.h \
%D%/lakemont.h \
%D%/x86_32_common.h \
%D%/stm8.h \
%D%/lakemont.h \
%D%/x86_32_common.h \
- %D%/arm_cti.h
+ %D%/arm_cti.h \
+ %D%/esirisc.h \
+ %D%/esirisc_jtag.h \
+ %D%/esirisc_regs.h
include %D%/openrisc/Makefile.am
include %D%/riscv/Makefile.am
include %D%/openrisc/Makefile.am
include %D%/riscv/Makefile.am