+#ifdef AO_MCO_PORT
+ cfgr = stm_rcc.cfgr;
+
+ /* Send PLL clock to MCO */
+ cfgr &= ~(STM_RCC_CFGR_MCO_MASK << STM_RCC_CFGR_MCO);
+ cfgr |= (STM_RCC_CFGR_MCO_PLLCLK << STM_RCC_CFGR_MCO);
+
+ /* Divide by 1 */
+ cfgr &= ~(STM_RCC_CFGR_MCOPRE_DIV_MASK << STM_RCC_CFGR_MCOPRE);
+ cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
+
+ /* Don't divide PLL */
+ cfgr |= (1 << STM_RCC_CFGR_PLL_NODIV);
+
+ stm_rcc.cfgr = cfgr;
+
+ ao_enable_port(AO_MCO_PORT);
+ stm_ospeedr_set(AO_MCO_PORT, AO_MCO_PIN, STM_OSPEEDR_HIGH);
+ stm_afr_set(AO_MCO_PORT, AO_MCO_PIN, AO_MCO_AF);
+#endif
+