+ .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
+ .description = "L1 Medium-Plus-density device",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff800cc,
+ .flash_pagesize = 0x100,
+ .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
+ .bootrom_base = 0x1ff00000,
+ .bootrom_size = 0x1000
+ },
+ {
+ .chip_id = STM32_CHIPID_L1_HIGH,
+ .description = "L1 High-density device",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff800cc,
+ .flash_pagesize = 0x100,
+ .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
+ .bootrom_base = 0x1ff00000,
+ .bootrom_size = 0x1000
+ },
+ {
+ .chip_id = STM32_CHIPID_L152_RE,
+ .description = "L152RE",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff800cc,
+ .flash_pagesize = 0x100,
+ .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
+ .bootrom_base = 0x1ff00000,
+ .bootrom_size = 0x1000
+ },
+ {
+ .chip_id = STM32_CHIPID_F1_CONN,
+ .description = "F1 Connectivity line device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x800,
+ .sram_size = 0x10000,
+ .bootrom_base = 0x1fffb000,
+ .bootrom_size = 0x4800
+ },
+ {//Low and Medium density VL have same chipid. RM0041 25.6.1
+ .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW,
+ .description = "F1 Medium/Low-density Value Line device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x400,
+ .sram_size = 0x2000,//0x1000 for low density devices
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ {
+ // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
+ .chip_id = STM32_CHIPID_F446,
+ .description = "F446 device",
+ .flash_type = FLASH_TYPE_F4,
+ .flash_size_reg = 0x1fff7a22,
+ .flash_pagesize = 0x20000,
+ .sram_size = 0x20000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
+ {
+ // This is STK32F303VCT6 device from STM32 F3 Discovery board.
+ // Support based on DM00043574.pdf (RM0316) document.
+ .chip_id = STM32_CHIPID_F3,
+ .description = "F3 device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc,
+ .flash_pagesize = 0x800,
+ .sram_size = 0xa000,
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ {
+ // This is STK32F373VCT6 device from STM32 F373 eval board
+ // Support based on 303 above (37x and 30x have same memory map)
+ .chip_id = STM32_CHIPID_F37x,
+ .description = "F3 device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc,
+ .flash_pagesize = 0x800,
+ .sram_size = 0xa000,
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ {
+ .chip_id = STM32_CHIPID_F1_VL_HIGH,
+ .description = "F1 High-density value line device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x800,
+ .sram_size = 0x8000,
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ {
+ .chip_id = STM32_CHIPID_F1_XL,
+ .description = "F1 XL-density device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x800,
+ .sram_size = 0x18000,
+ .bootrom_base = 0x1fffe000,
+ .bootrom_size = 0x1800
+ },
+ {
+ //Use this as an example for mapping future chips:
+ //RM0091 document was used to find these paramaters
+ .chip_id = STM32_CHIPID_F0_CAN,
+ .description = "F07x device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x800, // Page sizes listed in Table 4
+ .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
+ .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
+ .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
+ },
+ {
+ //Use this as an example for mapping future chips:
+ //RM0091 document was used to find these paramaters
+ .chip_id = STM32_CHIPID_F0,
+ .description = "F0 device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x400, // Page sizes listed in Table 4
+ .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
+ .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
+ .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
+ },
+ {
+ .chip_id = STM32_CHIPID_F09X,
+ .description = "F09X device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
+ .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
+ .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2
+ .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2
+ },
+ {
+ //Use this as an example for mapping future chips:
+ //RM0091 document was used to find these paramaters
+ .chip_id = STM32_CHIPID_F04,
+ .description = "F04x device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x400, // Page sizes listed in Table 4
+ .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
+ .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
+ .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2