- } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) {
-
- uint32_t val;
-
- /* check if the locks are set */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
- if((val & (1<<0))||(val & (1<<1))) {
- /* disable pecr protection */
- stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
- stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
-
- /* check pecr.pelock is cleared */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
- if (val & (1 << 0)) {
- WLOG("pecr.pelock not clear (%#x)\n", val);
- return -1;
- }
-
- /* unlock program memory */
- stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
- stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
-
- /* check pecr.prglock is cleared */
- val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
- if (val & (1 << 1)) {
- WLOG("pecr.prglock not clear (%#x)\n", val);
- return -1;
+ } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
+ || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
+ || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
+
+ uint32_t val;
+ uint32_t flash_regs_base;
+ if (sl->chip_id == STM32_CHIPID_L0) {
+ flash_regs_base = STM32L0_FLASH_REGS_ADDR;
+ } else {
+ flash_regs_base = STM32L_FLASH_REGS_ADDR;