+#if 0
+ fprintf(stderr, "%s:%d group registers in section, reg: %s (used: %d, %p)\n",
+ __FILE__, __LINE__, reg->name, reg->wasUsed, reg);
+#endif
+ if((reg->wasUsed
+ && !(reg->regop && SPEC_EXTR(OP_SYM_ETYPE(reg->regop))))
+ ) {
+
+ /* avoid grouping registers that have an initial value,
+ * they will be added later in idataSymSet */
+ if(reg->regop && (OP_SYMBOL(reg->regop)->ival && !OP_SYMBOL(reg->regop)->level))
+ continue;
+
+#if 0
+ fprintf(stderr, "%s:%d register %s alias:%d fix:%d ival=%i level=%i code=%i\n",
+ __FILE__, __LINE__, reg->name, reg->alias, reg->isFixed,
+ (reg->regop?(OP_SYMBOL(reg->regop)->ival?1:0):-1),
+ (reg->regop?(OP_SYMBOL(reg->regop)->level):-1),
+ (reg->regop?(IS_CODE(OP_SYM_ETYPE(reg->regop))):-1) );
+#endif
+
+ docontinue=0;
+ for(ssym=setFirstItem(sectSyms);ssym;ssym=setNextItem(sectSyms)) {
+ if(!strcmp(ssym->name, reg->name)) {
+// fprintf(stderr, "%s:%d section found %s (%p) with var %s\n",
+// __FILE__, __LINE__, ssym->section->name, ssym->section, ssym->name);
+ if(strcmp(ssym->section->name, "access")) {
+ addSet(&ssym->section->regsSet, reg);
+ docontinue=1;
+ break;
+ } else {
+ docontinue=0;
+ reg->accessBank = 1;
+ break;
+ }
+ }
+ }
+
+ if(docontinue)continue;
+
+// fprintf(stderr, "%s:%d reg: %s\n", __FILE__, __LINE__, reg->name);
+
+ if(reg->alias == 0x80) {
+ checkAddReg(&pic16_equ_data, reg);
+ } else
+ if(reg->isFixed) {
+ checkAddReg(&pic16_fix_udata, reg);
+ } else
+ if(!reg->isFixed) {
+ if(reg->pc_type == PO_GPR_TEMP)
+ checkAddReg(&pic16_int_regs, reg);
+ else {
+ if(reg->accessBank) {
+ if(reg->alias != 0x40)
+ checkAddReg(&pic16_acs_udata, reg);
+ } else
+ checkAddReg(&pic16_rel_udata, reg);
+ }
+ }
+ }
+ }