+ /*
+ * 4 SWCLK cycles with SWDIO low ...
+ * + SWD activation code 0x1a ...
+ * + at least 8 SWCLK cycles with SWDIO high
+ */
+ 0xa0, /* ((0x00) & GENMASK(3, 0)) | ((0x1a << 4) & GENMASK(7, 4)) */
+ 0xf1, /* ((0x1a >> 4) & GENMASK(3, 0)) | ((0xff << 4) & GENMASK(7, 4)) */
+ 0xff,
+ /* At least 50 SWCLK cycles with SWDIO high */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ /* At least 2 idle (low) cycles */
+ 0x00,
+};
+static const unsigned swd_seq_dormant_to_swd_len = 224;
+
+/**
+ * JTAG-to-dormant sequence.
+ *
+ * This is at least 5 TCK cycles with TMS high to put the interface
+ * in test-logic-reset state, followed by a specific 31-bit sequence.
+ * Bits are stored (and transmitted) LSB-first.
+ */
+static const uint8_t swd_seq_jtag_to_dormant[] = {
+ /* At least 5 TCK cycles with TMS high */
+ 0xff,
+ /*
+ * Still one TCK cycle with TMS high followed by 31 bits JTAG-to-DS
+ * select sequence 0xba, 0xbb, 0xbb, 0x33,
+ */
+ 0x75, /* ((0xff >> 7) & GENMASK(0, 0)) | ((0xba << 1) & GENMASK(7, 1)) */
+ 0x77, /* ((0xba >> 7) & GENMASK(0, 0)) | ((0xbb << 1) & GENMASK(7, 1)) */
+ 0x77, /* ((0xbb >> 7) & GENMASK(0, 0)) | ((0xbb << 1) & GENMASK(7, 1)) */
+ 0x67, /* ((0xbb >> 7) & GENMASK(0, 0)) | ((0x33 << 1) & GENMASK(7, 1)) */