+enum stm32_bank_id {
+ STM32_BANK1,
+ STM32_BANK2,
+ STM32_ALL_BANKS
+};
+
+struct stm32l4_wrp {
+ enum stm32l4_flash_reg_index reg_idx;
+ uint32_t value;
+ bool used;
+ int first;
+ int last;
+ int offset;
+};
+
+/* human readable list of families this drivers supports (sorted alphabetically) */
+static const char *device_families = "STM32G0/G4/L4/L4+/L5/WB/WL";
+
+static const struct stm32l4_rev stm32_415_revs[] = {
+ { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
+};
+
+static const struct stm32l4_rev stm32_435_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
+};
+
+static const struct stm32l4_rev stm32_460_revs[] = {
+ { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
+};
+
+static const struct stm32l4_rev stm32_461_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" },
+};
+
+static const struct stm32l4_rev stm32_462_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
+};
+
+static const struct stm32l4_rev stm32_464_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
+};
+
+static const struct stm32l4_rev stm32_466_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
+};
+
+static const struct stm32l4_rev stm32_468_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
+};
+
+static const struct stm32l4_rev stm32_469_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
+};
+
+static const struct stm32l4_rev stm32_470_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
+};
+
+static const struct stm32l4_rev stm32_471_revs[] = {
+ { 0x1001, "Z" },
+};
+
+static const struct stm32l4_rev stm32_472_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" },
+};
+
+static const struct stm32l4_rev stm32_479_revs[] = {
+ { 0x1000, "A" },
+};
+
+static const struct stm32l4_rev stm32_495_revs[] = {
+ { 0x2001, "2.1" },
+};
+
+static const struct stm32l4_rev stm32_496_revs[] = {
+ { 0x1000, "A" },
+};
+
+static const struct stm32l4_rev stm32_497_revs[] = {
+ { 0x1000, "1.0" },
+};
+
+static const struct stm32l4_part_info stm32l4_parts[] = {
+ {
+ .id = 0x415,
+ .revs = stm32_415_revs,
+ .num_revs = ARRAY_SIZE(stm32_415_revs),
+ .device_str = "STM32L47/L48xx",
+ .max_flash_size_kb = 1024,
+ .flags = F_HAS_DUAL_BANK,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x435,
+ .revs = stm32_435_revs,
+ .num_revs = ARRAY_SIZE(stm32_435_revs),
+ .device_str = "STM32L43/L44xx",
+ .max_flash_size_kb = 256,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x460,
+ .revs = stm32_460_revs,
+ .num_revs = ARRAY_SIZE(stm32_460_revs),
+ .device_str = "STM32G07/G08xx",
+ .max_flash_size_kb = 128,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x461,
+ .revs = stm32_461_revs,
+ .num_revs = ARRAY_SIZE(stm32_461_revs),
+ .device_str = "STM32L49/L4Axx",
+ .max_flash_size_kb = 1024,
+ .flags = F_HAS_DUAL_BANK,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x462,
+ .revs = stm32_462_revs,
+ .num_revs = ARRAY_SIZE(stm32_462_revs),
+ .device_str = "STM32L45/L46xx",
+ .max_flash_size_kb = 512,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x464,
+ .revs = stm32_464_revs,
+ .num_revs = ARRAY_SIZE(stm32_464_revs),
+ .device_str = "STM32L41/L42xx",
+ .max_flash_size_kb = 128,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x466,
+ .revs = stm32_466_revs,
+ .num_revs = ARRAY_SIZE(stm32_466_revs),
+ .device_str = "STM32G03/G04xx",
+ .max_flash_size_kb = 64,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x468,
+ .revs = stm32_468_revs,
+ .num_revs = ARRAY_SIZE(stm32_468_revs),
+ .device_str = "STM32G43/G44xx",
+ .max_flash_size_kb = 128,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x469,
+ .revs = stm32_469_revs,
+ .num_revs = ARRAY_SIZE(stm32_469_revs),
+ .device_str = "STM32G47/G48xx",
+ .max_flash_size_kb = 512,
+ .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x470,
+ .revs = stm32_470_revs,
+ .num_revs = ARRAY_SIZE(stm32_470_revs),
+ .device_str = "STM32L4R/L4Sxx",
+ .max_flash_size_kb = 2048,
+ .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x471,
+ .revs = stm32_471_revs,
+ .num_revs = ARRAY_SIZE(stm32_471_revs),
+ .device_str = "STM32L4P5/L4Q5x",
+ .max_flash_size_kb = 1024,
+ .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x472,
+ .revs = stm32_472_revs,
+ .num_revs = ARRAY_SIZE(stm32_472_revs),
+ .device_str = "STM32L55/L56xx",
+ .max_flash_size_kb = 512,
+ .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l5_ns_flash_regs,
+ .fsize_addr = 0x0BFA05E0,
+ .otp_base = 0x0BFA0000,
+ .otp_size = 512,
+ },
+ {
+ .id = 0x479,
+ .revs = stm32_479_revs,
+ .num_revs = ARRAY_SIZE(stm32_479_revs),
+ .device_str = "STM32G49/G4Axx",
+ .max_flash_size_kb = 512,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x495,
+ .revs = stm32_495_revs,
+ .num_revs = ARRAY_SIZE(stm32_495_revs),
+ .device_str = "STM32WB5x",
+ .max_flash_size_kb = 1024,
+ .flags = F_NONE,
+ .flash_regs_base = 0x58004000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x496,
+ .revs = stm32_496_revs,
+ .num_revs = ARRAY_SIZE(stm32_496_revs),
+ .device_str = "STM32WB3x",
+ .max_flash_size_kb = 512,
+ .flags = F_NONE,
+ .flash_regs_base = 0x58004000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+ {
+ .id = 0x497,
+ .revs = stm32_497_revs,
+ .num_revs = ARRAY_SIZE(stm32_497_revs),
+ .device_str = "STM32WLEx",
+ .max_flash_size_kb = 256,
+ .flags = F_NONE,
+ .flash_regs_base = 0x58004000,
+ .default_flash_regs = stm32l4_flash_regs,
+ .fsize_addr = 0x1FFF75E0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
+};
+
+/* flash bank stm32l4x <base> <size> 0 0 <target#> */