+/** set all FLASH_SECBB registers to the same value */
+static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
+{
+ /* This function should be used only with device with TrustZone, do just a security check */
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ assert(stm32l4_info->part_info->flags & F_HAS_TZ);
+
+ /* based on RM0438 Rev6 for STM32L5x devices:
+ * to modify a page block-based security attribution, it is recommended to
+ * 1- check that no flash operation is ongoing on the related page
+ * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
+ * this step is not need in case of JTAG direct access
+ */
+ int retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* write SECBBxRy registers */
+ LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
+
+ const uint8_t secbb_regs[] = {
+ FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
+ FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
+ };
+
+
+ unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
+
+ /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
+ * then consider only the first half of secbb_regs
+ */
+ if (!stm32l4_info->dual_bank_mode)
+ num_secbb_regs /= 2;
+
+ for (unsigned int i = 0; i < num_secbb_regs; i++) {
+ retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
+static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
+{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
+ STM32_FLASH_CR_WLK_INDEX : STM32_FLASH_CR_INDEX;
+}
+