+ int target_code_size = 0;
+ const uint32_t *target_code_src = NULL;
+
+ switch (bank->bus_width) {
+ case 2:
+ /* Check for DQ5 support */
+ if (cfi_info->status_poll_mask & (1 << 5)) {
+ target_code_src = mips_word_16_code;
+ target_code_size = sizeof(mips_word_16_code);
+ } else {
+ LOG_ERROR("Need DQ5 support");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ /* target_code_src = mips_word_16_code_dq7only; */
+ /* target_code_size = sizeof(mips_word_16_code_dq7only); */
+ }
+ break;
+ default:
+ LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
+ bank->bus_width);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ /* flash write code */
+ uint8_t *target_code;
+
+ /* convert bus-width dependent algorithm code to correct endianness */
+ target_code = malloc(target_code_size);
+ if (target_code == NULL) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+
+ target_buffer_set_u32_array(target, target_code, target_code_size / 4, target_code_src);
+
+ /* allocate working area */
+ retval = target_alloc_working_area(target, target_code_size,
+ &write_algorithm);
+ if (retval != ERROR_OK) {
+ free(target_code);
+ return retval;
+ }
+
+ /* write algorithm code to working area */
+ retval = target_write_buffer(target, write_algorithm->address,
+ target_code_size, target_code);
+ if (retval != ERROR_OK) {
+ free(target_code);
+ return retval;
+ }
+
+ free(target_code);
+
+ /* the following code still assumes target code is fixed 24*4 bytes */
+
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
+ buffer_size /= 2;
+ if (buffer_size <= 256) {
+ /* we already allocated the writing code, but failed to get a
+ * buffer, free the algorithm */
+ target_free_working_area(target, write_algorithm);
+
+ LOG_WARNING(
+ "not enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ }
+
+ init_reg_param(®_params[0], "r4", 32, PARAM_OUT);
+ init_reg_param(®_params[1], "r5", 32, PARAM_OUT);
+ init_reg_param(®_params[2], "r6", 32, PARAM_OUT);
+ init_reg_param(®_params[3], "r7", 32, PARAM_OUT);
+ init_reg_param(®_params[4], "r8", 32, PARAM_OUT);
+ init_reg_param(®_params[5], "r9", 32, PARAM_IN);
+ init_reg_param(®_params[6], "r12", 32, PARAM_OUT);
+ init_reg_param(®_params[7], "r13", 32, PARAM_OUT);
+ init_reg_param(®_params[8], "r14", 32, PARAM_OUT);
+ init_reg_param(®_params[9], "r15", 32, PARAM_OUT);
+
+ while (count > 0) {
+ uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
+
+ retval = target_write_buffer(target, source->address, thisrun_count, buffer);
+ if (retval != ERROR_OK)
+ break;
+
+ buf_set_u32(reg_params[0].value, 0, 32, source->address);
+ buf_set_u32(reg_params[1].value, 0, 32, address);
+ buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
+ buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
+ buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
+ buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
+ buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
+ buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
+ buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
+
+ retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
+ write_algorithm->address,
+ write_algorithm->address + ((target_code_size) - 4),
+ 10000, &mips32_info);
+ if (retval != ERROR_OK)
+ break;
+
+ status = buf_get_u32(reg_params[5].value, 0, 32);
+ if (status != 0x80) {
+ LOG_ERROR("flash write block failed status: 0x%" PRIx32, status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+
+ buffer += thisrun_count;
+ address += thisrun_count;
+ count -= thisrun_count;
+ }
+
+ target_free_all_working_areas(target);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+ destroy_reg_param(®_params[4]);
+ destroy_reg_param(®_params[5]);
+ destroy_reg_param(®_params[6]);
+ destroy_reg_param(®_params[7]);
+ destroy_reg_param(®_params[8]);
+ destroy_reg_param(®_params[9]);
+
+ return retval;
+}
+
+static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t address, uint32_t count)
+{
+ struct cfi_flash_bank *cfi_info = bank->driver_priv;
+ struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
+ struct target *target = bank->target;
+ struct reg_param reg_params[10];
+ void *arm_algo;
+ struct arm_algorithm armv4_5_algo;
+ struct armv7m_algorithm armv7m_algo;
+ struct working_area *write_algorithm;
+ struct working_area *source;
+ uint32_t buffer_size = 32768;
+ uint32_t status;
+ int retval = ERROR_OK;
+
+ /* input parameters -
+ * R0 = source address
+ * R1 = destination address
+ * R2 = number of writes
+ * R3 = flash write command
+ * R4 = constant to mask DQ7 bits (also used for Dq5 with shift)
+ * output parameters -
+ * R5 = 0x80 ok 0x00 bad
+ * temp registers -
+ * R6 = value read from flash to test status
+ * R7 = holding register
+ * unlock registers -
+ * R8 = unlock1_addr
+ * R9 = unlock1_cmd
+ * R10 = unlock2_addr
+ * R11 = unlock2_cmd */
+
+ /* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
+ static const uint32_t armv4_5_word_32_code[] = {
+ /* 00008100 <sp_32_code>: */