* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
static int lpc32xx_controller_ready(struct nand_device *nand, int timeout);
static int lpc32xx_tc_ready(struct nand_device *nand, int timeout);
extern int nand_correct_data(struct nand_device *nand, u_char *dat,
static int lpc32xx_controller_ready(struct nand_device *nand, int timeout);
static int lpc32xx_tc_ready(struct nand_device *nand, int timeout);
extern int nand_correct_data(struct nand_device *nand, u_char *dat,
/* These are offset with the working area in IRAM when using DMA to
* read/write data to the SLC controller.
/* These are offset with the working area in IRAM when using DMA to
* read/write data to the SLC controller.
if ((lpc32xx_info->osc_freq < 1000) || (lpc32xx_info->osc_freq > 20000))
LOG_WARNING("LPC32xx oscillator frequency should be between "
if ((lpc32xx_info->osc_freq < 1000) || (lpc32xx_info->osc_freq > 20000))
LOG_WARNING("LPC32xx oscillator frequency should be between "
- "1000 and 20000 kHz, was %i",
- lpc32xx_info->osc_freq);
+ "1000 and 20000 kHz, was %i",
+ lpc32xx_info->osc_freq);
retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
if (ERROR_OK != retval) {
LOG_ERROR("could not read HCLKPLL_CTRL");
retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
if (ERROR_OK != retval) {
LOG_ERROR("could not read HCLKPLL_CTRL");
- if ((address_cycles != 3) && (address_cycles != 4)) {
- LOG_ERROR("LPC32xx driver doesn't support %i", address_cycles);
+ if ((address_cycles < 3) || (address_cycles > 5)) {
+ LOG_ERROR("LPC32xx driver doesn't support %i address cycles", address_cycles);
/* select MLC controller if none is currently selected */
if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
LOG_DEBUG("no LPC32xx NAND flash controller selected, "
/* select MLC controller if none is currently selected */
if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
LOG_DEBUG("no LPC32xx NAND flash controller selected, "
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_TIME_REG");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_TIME_REG");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not set SLC_CFG");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not set SLC_CFG");
return ERROR_NAND_OPERATION_FAILED;
/* SLC_TAC: SLC timing arcs register */
retval = target_write_u32(target, 0x2002002c,
/* SLC_TAC: SLC timing arcs register */
retval = target_write_u32(target, 0x2002002c,
- (r_setup & 0xf)
- | ((r_hold & 0xf) << 4)
- | ((r_width & 0xf) << 8)
- | ((r_rdy & 0xf) << 12)
- | ((w_setup & 0xf) << 16)
- | ((w_hold & 0xf) << 20)
- | ((w_width & 0xf) << 24)
- | ((w_rdy & 0xf) << 28));
+ (r_setup & 0xf)
+ | ((r_hold & 0xf) << 4)
+ | ((r_width & 0xf) << 8)
+ | ((r_rdy & 0xf) << 12)
+ | ((w_setup & 0xf) << 16)
+ | ((w_hold & 0xf) << 20)
+ | ((w_width & 0xf) << 24)
+ | ((w_rdy & 0xf) << 28));
if (ERROR_OK != retval) {
LOG_ERROR("could not set SLC_TAC");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not set SLC_TAC");
return ERROR_NAND_OPERATION_FAILED;
if (!lpc32xx_controller_ready(nand, 100)) {
LOG_ERROR("LPC32xx MLC NAND controller timed out "
if (!lpc32xx_controller_ready(nand, 100)) {
LOG_ERROR("LPC32xx MLC NAND controller timed out "
return ERROR_NAND_OPERATION_TIMEOUT;
}
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
return ERROR_NAND_OPERATION_TIMEOUT;
}
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
- uint8_t *data, uint32_t data_size,
- uint8_t *oob, uint32_t oob_size)
+ uint8_t *data, uint32_t data_size,
+ uint8_t *oob, uint32_t oob_size)
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
if (nand->address_cycles == 4) {
retval = target_write_u32(target, 0x200b8004,
if (nand->address_cycles == 4) {
retval = target_write_u32(target, 0x200b8004,
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
if (!lpc32xx_controller_ready(nand, 1000)) {
LOG_ERROR("timeout while waiting for "
if (!lpc32xx_controller_ready(nand, 1000)) {
LOG_ERROR("timeout while waiting for "
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
if (status & NAND_STATUS_FAIL) {
LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
if (status & NAND_STATUS_FAIL) {
LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
{
uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
{
uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
Terminal count interrupt enable bit = 0
*/
ecc_ctrl = 0x01 | 1 << 12 | 1 << 15 | 2 << 18 | 2 << 21 | 0 << 24
Terminal count interrupt enable bit = 0
*/
ecc_ctrl = 0x01 | 1 << 12 | 1 << 15 | 2 << 18 | 2 << 21 | 0 << 24
- ctrl |= 1 << 27; /* Destination increment = 1 */
- oob_ctrl |= 1 << 27; /* Destination increment = 1 */
- dmasrc = 0x20020038; /* SLC_DMA_DATA */
+ ctrl |= 1 << 27;/* Destination increment = 1 */
+ oob_ctrl |= 1 << 27; /* Destination increment = 1 */
+ dmasrc = 0x20020038; /* SLC_DMA_DATA */
dmalist[i*2].dma_src = (do_read ? dmasrc : (dmasrc + i * 256));
dmalist[i*2].dma_dest = (do_read ? (dmadst + i * 256) : dmadst);
dmalist[i*2].next_lli =
target_mem_base + (i*2 + 1) * sizeof(dmac_ll_t);
dmalist[i*2].next_ctrl = ctrl;
dmalist[i*2].dma_src = (do_read ? dmasrc : (dmasrc + i * 256));
dmalist[i*2].dma_dest = (do_read ? (dmadst + i * 256) : dmadst);
dmalist[i*2].next_lli =
target_mem_base + (i*2 + 1) * sizeof(dmac_ll_t);
dmalist[i*2].next_ctrl = ctrl;
dmalist[(i*2) + 1].dma_dest =
target_mem_base + ECC_OFFS + i * 4;
dmalist[(i*2) + 1].next_lli =
dmalist[(i*2) + 1].dma_dest =
target_mem_base + ECC_OFFS + i * 4;
dmalist[(i*2) + 1].next_lli =
- dmalist[(i*2) - 1].next_lli = 0; /* last link = null on write */
- dmalist[(i*2) - 1].next_ctrl |= (1 << 31); /* Set TC enable */
+ dmalist[(i*2) - 1].next_lli = 0;/* last link = null on write */
+ dmalist[(i*2) - 1].next_ctrl |= (1 << 31); /* Set TC enable */
}
dmalist[i*2].dma_src = dmasrc;
dmalist[i*2].dma_dest = dmadst;
dmalist[i*2].next_lli = 0;
dmalist[i*2].next_ctrl = oob_ctrl;
}
dmalist[i*2].dma_src = dmasrc;
dmalist[i*2].dma_dest = dmadst;
dmalist[i*2].next_lli = 0;
dmalist[i*2].next_ctrl = oob_ctrl;
/* DMACIntErrClear = ch0 */
retval = target_write_u32(target, 0x31000010, 1);
if (ERROR_OK != retval) {
LOG_ERROR("Could not set DMACIntErrClear");
return retval;
}
/* DMACIntErrClear = ch0 */
retval = target_write_u32(target, 0x31000010, 1);
if (ERROR_OK != retval) {
LOG_ERROR("Could not set DMACIntErrClear");
return retval;
}
}
if ((tc_stat | err_stat) & 1) {
LOG_DEBUG("lpc32xx_dma_ready count=%d",
}
if ((tc_stat | err_stat) & 1) {
LOG_DEBUG("lpc32xx_dma_ready count=%d",
-static uint32_t slc_ecc_copy_to_buffer(uint8_t * spare,
- const uint32_t * ecc, int count)
+static uint32_t slc_ecc_copy_to_buffer(uint8_t *spare,
+ const uint32_t *ecc, int count)
- oob[0], oob[1], oob[2], oob[3],
- oob[4], oob[5], oob[6], oob[7]);
+ oob[0], oob[1], oob[2], oob[3],
+ oob[4], oob[5], oob[6], oob[7]);
- struct working_area *pworking_area,
- uint32_t page, uint8_t *data,
- uint32_t data_size, uint8_t *oob,
- uint32_t oob_size)
+ struct working_area *pworking_area,
+ uint32_t page, uint8_t *data,
+ uint32_t data_size, uint8_t *oob,
+ uint32_t oob_size)
- LOG_DEBUG("SLC write page %x data=%d, oob=%d, "
- "data_size=%d, oob_size=%d",
- page, data != 0, oob != 0, data_size, oob_size);
+ LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, "
+ "data_size=%" PRIu32 ", oob_size=%" PRIu32,
+ page, data != 0, oob != 0, data_size, oob_size);
}
/* Make the dma descriptors in local memory */
int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 0);
}
/* Make the dma descriptors in local memory */
int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 0);
XXX: Assumes host and target have same byte sex.
*/
retval = target_write_memory(target, target_mem_base, 4,
XXX: Assumes host and target have same byte sex.
*/
retval = target_write_memory(target, target_mem_base, 4,
*/
retval = target_write_u32(target, 0x20020014, 0x3c);
if (ERROR_OK != retval) {
*/
retval = target_write_u32(target, 0x20020014, 0x3c);
if (ERROR_OK != retval) {
memset(fdata, 0xFF, nand->page_size);
memcpy(fdata, data, data_size);
retval = target_write_memory(target,
memset(fdata, 0xFF, nand->page_size);
memcpy(fdata, data, data_size);
retval = target_write_memory(target,
- target_mem_base + DATA_OFFS,
- 4, nand->page_size/4, fdata);
+ target_mem_base + DATA_OFFS,
+ 4, nand->page_size/4, fdata);
/* Write first decriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
/* Write first decriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
/* Wait for DMA to finish. SLC is not finished at this stage */
if (!lpc32xx_dma_ready(nand, 100)) {
LOG_ERROR("Data DMA failed during write");
return ERROR_FLASH_OPERATION_FAILED;
}
/* Wait for DMA to finish. SLC is not finished at this stage */
if (!lpc32xx_dma_ready(nand, 100)) {
LOG_ERROR("Data DMA failed during write");
return ERROR_FLASH_OPERATION_FAILED;
}
/* Copy OOB to iram */
static uint8_t foob[64];
int foob_size = nand->page_size == 2048 ? 64 : 16;
memset(foob, 0xFF, foob_size);
/* Copy OOB to iram */
static uint8_t foob[64];
int foob_size = nand->page_size == 2048 ? 64 : 16;
memset(foob, 0xFF, foob_size);
/* Get HW generated ECC, made while writing data */
int ecc_count = nand->page_size == 2048 ? 8 : 2;
static uint32_t hw_ecc[8];
retval = target_read_memory(target, target_mem_base + ECC_OFFS,
/* Get HW generated ECC, made while writing data */
int ecc_count = nand->page_size == 2048 ? 8 : 2;
static uint32_t hw_ecc[8];
retval = target_read_memory(target, target_mem_base + ECC_OFFS,
/* Copy to oob, at correct offsets */
static uint8_t ecc[24];
slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
/* Copy to oob, at correct offsets */
static uint8_t ecc[24];
slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
int i;
for (i = 0; i < ecc_count * 3; i++)
foob[layout[i]] = ecc[i];
lpc32xx_dump_oob(foob, foob_size);
}
retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
int i;
for (i = 0; i < ecc_count * 3; i++)
foob[layout[i]] = ecc[i];
lpc32xx_dump_oob(foob, foob_size);
}
retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
/* Write OOB decriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
/* Write OOB decriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
- E=1,
- SrcPeripheral = 1 (SLC),
- DestPeripheral = 1 (SLC),
- FlowCntrl = 2 (Pher -> Mem, DMA),
- IE = 0,
- ITC = 0,
- L= 0,
- H=0
+ * E=1,
+ * SrcPeripheral = 1 (SLC),
+ * DestPeripheral = 1 (SLC),
+ * FlowCntrl = 2 (Pher -> Mem, DMA),
+ * IE = 0,
+ * ITC = 0,
+ * L= 0,
+ * H=0
/* Wait finish */
if (!lpc32xx_tc_ready(nand, 100)) {
LOG_ERROR("timeout while waiting for "
/* Wait finish */
if (!lpc32xx_tc_ready(nand, 100)) {
LOG_ERROR("timeout while waiting for "
- uint8_t *data, uint32_t data_size,
- uint8_t *oob, uint32_t oob_size)
+ uint8_t *data, uint32_t data_size,
+ uint8_t *oob, uint32_t oob_size)
{
struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
struct target *target = nand->target;
{
struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
struct target *target = nand->target;
} else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
if (!data && oob) {
LOG_ERROR("LPC32xx MLC controller can't write "
} else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
if (!data && oob) {
LOG_ERROR("LPC32xx MLC controller can't write "
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
if (oob && (oob_size > 24)) {
LOG_ERROR("LPC32xx MLC controller can't write more "
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
if (oob && (oob_size > 24)) {
LOG_ERROR("LPC32xx MLC controller can't write more "
}
retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
}
retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
struct working_area *pworking_area;
if (!data && oob) {
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
struct working_area *pworking_area;
if (!data && oob) {
* Anyway the code supports the oob only mode below.
*/
return nand_write_page_raw(nand, page, data,
* Anyway the code supports the oob only mode below.
*/
return nand_write_page_raw(nand, page, data,
return ERROR_FLASH_OPERATION_FAILED;
}
retval = lpc32xx_write_page_slc(nand, pworking_area, page,
return ERROR_FLASH_OPERATION_FAILED;
}
retval = lpc32xx_write_page_slc(nand, pworking_area, page,
- data, data_size, oob, oob_size);
+ data, data_size, oob, oob_size);
- uint8_t *data, uint32_t data_size,
- uint8_t *oob, uint32_t oob_size)
+ uint8_t *data, uint32_t data_size,
+ uint8_t *oob, uint32_t oob_size)
retval = target_write_u32(target, 0x200b8004, 0x0);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
retval = target_write_u32(target, 0x200b8004, 0x0);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
if (nand->address_cycles == 4) {
retval = target_write_u32(target, 0x200b8004,
if (nand->address_cycles == 4) {
retval = target_write_u32(target, 0x200b8004,
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
}
} else {
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
}
} else {
retval = target_write_u32(target, 0x200b8004, 0x0);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
retval = target_write_u32(target, 0x200b8004, 0x0);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
/* MLC_CMD = Read Start */
retval = target_write_u32(target, 0x200b8000,
/* MLC_CMD = Read Start */
retval = target_write_u32(target, 0x200b8000,
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
if (!lpc32xx_controller_ready(nand, 1000)) {
LOG_ERROR("timeout while waiting for "
if (!lpc32xx_controller_ready(nand, 1000)) {
LOG_ERROR("timeout while waiting for "
return ERROR_NAND_OPERATION_FAILED;
}
LOG_WARNING("%i symbol error detected and corrected",
return ERROR_NAND_OPERATION_FAILED;
}
LOG_WARNING("%i symbol error detected and corrected",
}
if (data) {
retval = target_read_memory(target, 0x200a8000, 4, 128,
}
if (data) {
retval = target_read_memory(target, 0x200a8000, 4, 128,
if (ERROR_OK != retval) {
LOG_ERROR("could not read MLC_BUF (data)");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not read MLC_BUF (data)");
return ERROR_NAND_OPERATION_FAILED;
if (oob) {
retval = target_read_memory(target, 0x200a8000, 4, 4,
if (oob) {
retval = target_read_memory(target, 0x200a8000, 4, 4,
if (ERROR_OK != retval) {
LOG_ERROR("could not read MLC_BUF (oob)");
return ERROR_NAND_OPERATION_FAILED;
if (ERROR_OK != retval) {
LOG_ERROR("could not read MLC_BUF (oob)");
return ERROR_NAND_OPERATION_FAILED;
- struct working_area *pworking_area,
- uint32_t page, uint8_t *data,
- uint32_t data_size, uint8_t *oob,
- uint32_t oob_size)
+ struct working_area *pworking_area,
+ uint32_t page, uint8_t *data,
+ uint32_t data_size, uint8_t *oob,
+ uint32_t oob_size)
- LOG_DEBUG("SLC read page %x data=%d, oob=%d",
- page, data_size, oob_size);
+ LOG_DEBUG("SLC read page %" PRIx32 " data=%" PRIu32 ", oob=%" PRIu32,
+ page, data_size, oob_size);
XXX: Assumes host and target have same byte sex.
*/
retval = target_write_memory(target, target_mem_base, 4,
XXX: Assumes host and target have same byte sex.
*/
retval = target_write_memory(target, target_mem_base, 4,
*/
retval = target_write_u32(target, 0x20020014, 0x3e);
if (ERROR_OK != retval) {
*/
retval = target_write_u32(target, 0x20020014, 0x3e);
if (ERROR_OK != retval) {
/* Write first decriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
/* Write first decriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
/* Copy data from iram */
if (data) {
retval = target_read_memory(target, target_mem_base + DATA_OFFS,
/* Copy data from iram */
if (data) {
retval = target_read_memory(target, target_mem_base + DATA_OFFS,
if (oob) {
/* No error correction, just return data as read from flash */
retval = target_read_memory(target,
if (oob) {
/* No error correction, just return data as read from flash */
retval = target_read_memory(target,
/* Copy OOB from flash, stored in IRAM */
static uint8_t foob[64];
retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
/* Copy OOB from flash, stored in IRAM */
static uint8_t foob[64];
retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
if (ERROR_OK != retval) {
LOG_ERROR("Could not read OOB from IRAM");
lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
if (ERROR_OK != retval) {
LOG_ERROR("Could not read OOB from IRAM");
}
/* Copy ECC from HW, generated while reading */
int ecc_count = nand->page_size == 2048 ? 8 : 2;
}
/* Copy ECC from HW, generated while reading */
int ecc_count = nand->page_size == 2048 ? 8 : 2;
retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
static uint8_t ecc[24];
slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
/* Copy ECC from flash using correct layout */
static uint8_t ecc[24];
slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
/* Copy ECC from flash using correct layout */
- static uint8_t fecc[24]; /* max size */
- int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
+ static uint8_t fecc[24];/* max size */
+ const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
int i;
for (i = 0; i < ecc_count * 3; i++)
fecc[i] = foob[layout[i]];
/* Compare ECC and possibly correct data */
for (i = 0; i < ecc_count; i++) {
retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3],
int i;
for (i = 0; i < ecc_count * 3; i++)
fecc[i] = foob[layout[i]];
/* Compare ECC and possibly correct data */
for (i = 0; i < ecc_count; i++) {
retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3],
retval = ERROR_NAND_OPERATION_FAILED;
}
return retval;
}
static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
retval = ERROR_NAND_OPERATION_FAILED;
}
return retval;
}
static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
- uint8_t *data, uint32_t data_size,
- uint8_t *oob, uint32_t oob_size)
+ uint8_t *data, uint32_t data_size,
+ uint8_t *oob, uint32_t oob_size)
{
struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
struct target *target = nand->target;
{
struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
struct target *target = nand->target;
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
struct working_area *pworking_area;
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
struct working_area *pworking_area;
- retval = target_alloc_working_area(target,
- nand->page_size + 0x200,
- &pworking_area);
+ retval = target_alloc_working_area(target,
+ nand->page_size + 0x200,
+ &pworking_area);
return ERROR_FLASH_OPERATION_FAILED;
}
retval = lpc32xx_read_page_slc(nand, pworking_area, page,
return ERROR_FLASH_OPERATION_FAILED;
}
retval = lpc32xx_read_page_slc(nand, pworking_area, page,
- data, data_size, oob, oob_size);
- target_free_working_area(target, pworking_area);
+ data, data_size, oob, oob_size);
+ target_free_working_area(target, pworking_area);
unsigned num;
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
struct nand_device *nand = get_nand_device_by_num(num);
if (!nand) {
command_print(CMD_CTX, "nand device '#%s' is out of bounds",
unsigned num;
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
struct nand_device *nand = get_nand_device_by_num(num);
if (!nand) {
command_print(CMD_CTX, "nand device '#%s' is out of bounds",
} else if (strcmp(CMD_ARGV[1], "slc") == 0) {
lpc32xx_info->selected_controller =
LPC32xx_SLC_CONTROLLER;
} else if (strcmp(CMD_ARGV[1], "slc") == 0) {
lpc32xx_info->selected_controller =
LPC32xx_SLC_CONTROLLER;
.chain = lpc32xx_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
.chain = lpc32xx_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE