-/*
- * Simulating timers
- *
- * Calling inherited method to simulate timer #0 and #1 and then
- * simulating timer #2.
- *
- */
-
-/*void
-t_uc52::do_extra_hw(int cycles)
-{
- do_timer2(cycles);
-}*/
-
-
-/*
- * Simulating timer 2
- */
-
-/*int
-t_uc52::do_timer2(int cycles)
-{
- bool nocount= DD_FALSE;
- uint t2con= get_mem(MEM_SFR, T2CON);
-
- exf2it->activate();
- if (!(t2con & bmTR2))
- // Timer OFF
- return(resGO);
-
- if (t2con & (bmRCLK | bmTCLK))
- return(do_t2_baud(cycles));
-
- // Determining nr of input clocks
- if (!(t2con & bmTR2))
- nocount= DD_TRUE; // Timer OFF
- else
- if (t2con & bmC_T2)
- {
- // Counter mode, falling edge on P1.0 (T2)
- if ((prev_p1 & bmT2) &&
- !(sfr->read(P1) & bmT2))
- cycles= 1;
- else
- nocount= DD_TRUE;
- }
- // Counting
- while (cycles--)
- {
- if (t2con & bmCP_RL2)
- do_t2_capture(&cycles, nocount);
- else
- do_t2_reload(&cycles, nocount);
- }// while cycles
-
- return(resGO);
-}*/
-
-
-/*
- * Baud rate generator mode of Timer #2
- */
-
-/*int
-t_uc52::do_t2_baud(int cycles)
-{
- t_mem t2con= sfr->get(T2CON);
- //uint p1= get_mem(MEM_SFR, P1);
-
- // Baud Rate Generator
- if ((prev_p1 & bmT2EX) &&
- !(sfr->read(P1) & bmT2EX) &&
- (t2con & bmEXEN2))
- mem(MEM_SFR)->set_bit1(T2CON, bmEXF2);
- if (t2con & bmC_T2)
- {
- if ((prev_p1 & bmT2) &&
- !(sfr->read(P1) & bmT2))
- cycles= 1;
- else
- cycles= 0;
- }
- else
- cycles*= 6;
- if (t2con & bmTR2)
- while (cycles--)
- {
- if (!sfr->add(TL2, 1))
- if (!sfr->add(TH2, 1))
- {
- sfr->set(TH2, sfr->get(RCAP2H));
- sfr->set(TL2, sfr->get(RCAP2L));
- s_rec_t2++;
- s_tr_t2++;
- }
- }
- return(resGO);
-}*/
-
-
-/*
- * Capture function of Timer #2
- */
-
-/*void
-t_uc52::do_t2_capture(int *cycles, bool nocount)
-{
- //uint p1= get_mem(MEM_SFR, P1);
- t_mem t2con= sfr->get(T2CON);
-
- // Capture mode
- if (nocount)
- *cycles= 0;
- else
- {
- if (!sfr->add(TL2, 1))
- {
- if (!sfr->add(TH2, 1))
- mem(MEM_SFR)->set_bit1(T2CON, bmTF2);
- }
- }
- // capture
- if ((prev_p1 & bmT2EX) &&
- !(sfr->read(P1) & bmT2EX) &&
- (t2con & bmEXEN2))
- {
- sfr->set(RCAP2H, sfr->get(TH2));
- sfr->set(RCAP2L, sfr->get(TL2));
- mem(MEM_SFR)->set_bit1(T2CON, bmEXF2);
- prev_p1&= ~bmT2EX; // Falling edge has been handled
- }
-}*/
-
-
-/*
- * Auto Reload mode of Timer #2, counting UP
- */
-
-/*void
-t_uc52::do_t2_reload(int *cycles, bool nocount)
-{
- int overflow;
- bool ext2= 0;
-
- // Auto-Relode mode
- overflow= 0;
- if (nocount)
- *cycles= 0;
- else
- {
- if (!sfr->add(TL2, 1))
- {
- if (!sfr->add(TH2, 1))
- {
- sfr->set_bit1(T2CON, bmTF2);
- overflow++;
- }
- }
- }
- // reload
- if ((prev_p1 & bmT2EX) &&
- !(sfr->read(P1) & bmT2EX) &&
- (sfr->get(T2CON) & bmEXEN2))
- {
- ext2= DD_TRUE;
- sfr->set_bit1(T2CON, bmEXF2);
- prev_p1&= ~bmT2EX; // Falling edge has been handled
- }
- if (overflow ||
- ext2)
- {
- sfr->set(TH2, sfr->get(RCAP2H));
- sfr->set(TL2, sfr->get(RCAP2L));
- }
-}*/
-
-
-/*
- *
- */
-
-/*int
-t_uc52::serial_bit_cnt(int mode)
-{
- int divby= 12;
- int *tr_src= 0, *rec_src= 0;
-
- switch (mode)
- {
- case 0:
- divby = 12;
- tr_src = &s_tr_tick;
- rec_src= &s_rec_tick;
- break;
- case 1:
- case 3:
- divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32;
- tr_src = (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_tr_t2):(&s_tr_t1);
- rec_src= (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_rec_t2):(&s_rec_t1);
- break;
- case 2:
- divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32;
- tr_src = &s_tr_tick;
- rec_src= &s_rec_tick;
- break;
- }
- if (s_sending)
- {
- while (*tr_src >= divby)
- {
- (*tr_src)-= divby;
- s_tr_bit++;
- }
- }
- if (s_receiving)
- {
- while (*rec_src >= divby)
- {
- (*rec_src)-= divby;
- s_rec_bit++;
- }
- }
- return(0);
-}*/
-
-