-/*
- * Processing write operation of SFR
- *
- * Inherited method is extended with WDT handling.
- */
-
-void
-t_uc51r::proc_write(uchar *addr)
-{
- t_uc52::proc_write(addr);
- // Handling WDT
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[WDTRST]))
- {
- if ((wdtrst == 0x1e) &&
- (*addr == 0xe1))
- {
- WDT= 0;
- sim->app->get_commander()->
- debug("%g sec (%d tick): Watchdog timer enabled/reset PC= 0x%06x"
- "\n", get_rtime(), ticks->ticks, PC);
- }
- wdtrst= *addr;
- }
-}
-
-
-/*
- * Simulating timers
- *
- * Calling inherited method to simulate timer #0 and #1 and then
- * simulating timer #2.
- */
-
-int
-t_uc51r::do_timers(int cycles)
-{
- int res;
-
- if ((res= t_uc51::do_timers(cycles)) != resGO)
- return(res);
- return(do_timer2(cycles));
-}
-
-
-/*
- * Simulating timer 2
- *
- * It is something wrong: T2MOD is not implemented in 52?!
- */
-
-int
-t_uc51r::do_timer2(int cycles)
-{
- bool nocount= DD_FALSE;
- uint t2mod= get_mem(MEM_SFR, T2MOD);
- uint t2con= get_mem(MEM_SFR, T2CON);
- uint p1= get_mem(MEM_SFR, P1);
-
- exf2it->activate();
- if (!(t2con & bmTR2))
- /* Timer OFF */
- return(resGO);
-
- if (t2mod & bmT2OE)
- return(do_t2_clockout(cycles));
-
- if (t2con & (bmRCLK | bmTCLK))
- return(do_t2_baud(cycles));
-
- /* Determining nr of input clocks */
- if (!(t2con & bmTR2))
- nocount= DD_TRUE; // Timer OFF
- else
- if (t2con & bmC_T2)
- {
- // Counter mode, falling edge on P1.0 (T2)
- if ((prev_p1 & bmT2) &&
- !(p1 & port_pins[1] & bmT2))
- cycles= 1;
- else
- nocount= DD_TRUE;
- }
- /* Counting */
- while (cycles--)
- {
- if (t2con & bmCP_RL2)
- do_t2_capture(&cycles, nocount);
- else
- {
- int overflow;
- overflow= 0;
- /* Auto-Relode mode */
- if (t2mod & bmDCEN)
- {
- /* DCEN= 1 */
- exf2it->deactivate();
- if (nocount)
- cycles= 0;
- else
- {
- if (p1 & port_pins[1] & bmT2EX)
- {
- // UP
- if (!/*++(MEM(MEM_SFR)[TL2])*/sfr->add(TL2, 1))
- if (!/*++(MEM(MEM_SFR)[TH2])*/sfr->add(TH2, 1))
- {
- overflow++;
- //MEM(MEM_SFR)[TH2]= MEM(MEM_SFR)[RCAP2H];
- sfr->set(TH2, sfr->get(RCAP2H));
- //MEM(MEM_SFR)[TL2]= MEM(MEM_SFR)[RCAP2L];
- sfr->set(TL2, sfr->get(RCAP2L));
- mem(MEM_SFR)->set_bit1(T2CON, bmTF2);
- }
- }
- else
- {
- // DOWN
- //MEM(MEM_SFR)[TL2]--;
- if (/*MEM(MEM_SFR)[TL2]*/sfr->add(TL2, -1) == 0xff)
- /*MEM(MEM_SFR)[TH2]--*/sfr->add(TH2, -1);
- /*if (MEM(MEM_SFR)[TH2] == MEM(MEM_SFR)[RCAP2H] &&
- MEM(MEM_SFR)[TL2] == MEM(MEM_SFR)[RCAP2L])*/
- if (sfr->get(TH2) == sfr->get(RCAP2H) &&
- sfr->get(TL2) == sfr->get(RCAP2L))
- {
- overflow++;
- //MEM(MEM_SFR)[TH2]= MEM(MEM_SFR)[TL2]= 0xff;
- sfr->set(TH2, 0xff);
- sfr->set(TL2, 0xff);
- mem(MEM_SFR)->set_bit1(T2CON, bmTF2);
- }
- }
- while (overflow--)
- //MEM(MEM_SFR)[P1]^= bmEXF2;
- sfr->set(P1, sfr->get(P1) ^ bmEXF2);
- }
- }
- else
- /* DCEN= 0 */
- do_t2_reload(&cycles, nocount);
- }
- }// while cycles
-
- return(resGO);
-}
-
-
-/*
- * Clock out mode of Timer #2
- */
-
-int
-t_uc51r::do_t2_clockout(int cycles)
-{
- uint t2con= get_mem(MEM_SFR, T2CON);
- uint p1= get_mem(MEM_SFR, P1);
-
- /* Programmable Clock Out Mode */
- if ((prev_p1 & bmT2EX) &&
- !(p1 & port_pins[1] & bmT2EX) &&
- (t2con & bmEXEN2))
- mem(MEM_SFR)->set_bit1(T2CON, bmEXF2);
- if (t2con & bmCP_RL2)
- return(resGO);
- if (t2con & bmC_T2)
- {
- if ((prev_p1 & bmT2) &&
- !(p1 & port_pins[1] & bmT2))
- cycles= 1;
- else
- cycles= 0;
- }
- else
- cycles*= 6;
- if (t2con & bmTR2)
- while (cycles--)
- {
- if (!/*++(MEM(MEM_SFR)[TL2])*/sfr->add(TL2, 1))
- if (!/*++(MEM(MEM_SFR)[TH2])*/sfr->add(TH2, 1))
- {
- //MEM(MEM_SFR)[TH2]= MEM(MEM_SFR)[RCAP2H];
- sfr->set(TH2, sfr->get(RCAP2H));
- //MEM(MEM_SFR)[TL2]= MEM(MEM_SFR)[RCAP2L];
- sfr->set(TL2, sfr->get(RCAP2L));
- clock_out++;
- if (!(t2con & bmC_T2))
- {
- SET_BIT((clock_out&1), P1, bmT2);
- }
- }
- }
- return(resGO);
-}
-
-
-/*
- * Handling serial line
- */
-
-int
-t_uc51r::serial_bit_cnt(int mode)
-{
- int divby= 12;
- int *tr_src= 0, *rec_src= 0;
-
- switch (mode)
- {
- case 0:
- divby = 12;
- tr_src = &s_tr_tick;
- rec_src= &s_rec_tick;
- break;
- case 1:
- case 3:
- divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32;
- tr_src = (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_tr_t2):(&s_tr_t1);
- rec_src= (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_rec_t2):(&s_rec_t1);
- break;
- case 2:
- divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32;
- tr_src = &s_tr_tick;
- rec_src= &s_rec_tick;
- break;
- }
- if (s_sending)
- {
- while (*tr_src >= divby)
- {
- (*tr_src)-= divby;
- s_tr_bit++;
- }
- }
- if (s_receiving)
- {
- while (*rec_src >= divby)
- {
- (*rec_src)-= divby;
- s_rec_bit++;
- }
- }
- return(0);
-}
-