+/*
+ * Setting up SFR area to reset value
+ */
+
+void
+t_uc390::clear_sfr(void)
+{
+ int i;
+
+ for (i = 0; i < SFR_SIZE; i++)
+ sfr->set(i, 0);
+ /* SFR value */
+ sfr->set(0x80, 0xff); /* P4 */
+ sfr->set(0x81, 0x07); /* SP */
+ sfr->set(0x86, 0x04); /* DPS */
+ sfr->set(0x90, 0xff); /* P1 */
+ sfr->set(0x92, 0xbf); /* P4CNT */
+ sfr->set(0x9b, 0xfc); /* ESP */
+ if (flat24_flag)
+ sfr->set(ACON, 0xfa); /* ACON; AM1 set: 24-bit flat */
+ else
+ sfr->set(ACON, 0xf8); /* ACON */
+ sfr->set(0xa0, 0xff); /* P2 */
+ sfr->set(0xa1, 0xff); /* P5 */
+ sfr->set(0xa3, 0x09); /* COC */
+ sfr->set(0xb0, 0xff); /* P3 */
+ sfr->set(0xb8, 0x80); /* IP */
+ sfr->set(0xc5, 0x10); /* STATUS */
+ sfr->set(0xc6, 0x10); /* MCON */
+ sfr->set(0xc7, 0xff); /* TA */
+ sfr->set(0xc9, 0xe4); /* T2MOD */
+ sfr->set(0xd2, 0x2f); /* MCNT1 */
+ sfr->set(0xe3, 0x09); /* C1C */
+
+ sfr->/*set*/write(P0, 0xff);
+ sfr->/*set*/write(P1, 0xff);
+ sfr->/*set*/write(P2, 0xff);
+ sfr->/*set*/write(P3, 0xff);
+ sfr->/*set*/write(SP, 7);
+ prev_p1 = sfr->/*get*/read(P1);
+ prev_p3 = sfr->/*get*/read(P3);
+}