projects
/
hw
/
altusmetrum
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
clean up SAMD21G symbol to eliminate bogus inherited attributes
[hw/altusmetrum]
/
pcb-rnd.mk
diff --git
a/pcb-rnd.mk
b/pcb-rnd.mk
index d630ec12b41a9db6e61172604dbb5119b930e11a..a574b804490a76f9d364db8f325f01ad09168326 100644
(file)
--- a/
pcb-rnd.mk
+++ b/
pcb-rnd.mk
@@
-1,7
+1,7
@@
AM=../altusmetrum
SCHEME=$(AM)/scheme
AM=../altusmetrum
SCHEME=$(AM)/scheme
-.SUFFIXES: .lht .sch .ps .pdf .tdx
+.SUFFIXES: .lht .sch .ps .pdf .tdx
.scad .stl
# need to have PROJECT defined
ifndef PROJECT
# need to have PROJECT defined
ifndef PROJECT
@@
-101,6
+101,12
@@
stencilsunlimited: $(BOTTOMCOPPER) $(PROJECT).toppaste.gbr $(OUTLINE)
stencil: $(PROJECT).lht
pcb-rnd -x cam gerber:stencils --outfile out/$(PROJECT) $(PROJECT).lht
stencil: $(PROJECT).lht
pcb-rnd -x cam gerber:stencils --outfile out/$(PROJECT) $(PROJECT).lht
+$(PROJECT).scad: $(PROJECT).lht
+ pcb-rnd -x openscad $(PROJECT).lht
+
+$(PROJECT).stl: $(PROJECT).scad
+ openscad --o $(PROJECT).stl $(PROJECT).scad
+
clean:
rm -f *.bom *.drc *.log *~ $(PROJECT).ps *.gbr *.cnc *bak* *- *.zip *.tdx *.backup
rm -f *.net *.xy *.cmd *.png partslist partslist.csv *.ger *.xln PCB*save
clean:
rm -f *.bom *.drc *.log *~ $(PROJECT).ps *.gbr *.cnc *bak* *- *.zip *.tdx *.backup
rm -f *.net *.xy *.cmd *.png partslist partslist.csv *.ger *.xln PCB*save