- setting_reg #(`FR_RADAR_FREQ1N) sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(freq_o));
+ setting_reg #(`FR_RADAR_FINCR) sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(fincr_o));
+
+ // Pulse state machine
+ `define ST_ON 4'b0001
+ `define ST_SW 4'b0010
+ `define ST_LOOK 4'b0100
+ `define ST_IDLE 4'b1000
+
+ reg [3:0] state;
+ reg [31:0] count;
+
+ always @(posedge clk_i)
+ if (reset_o)
+ begin
+ state <= `ST_ON;
+ count <= 32'b0;
+ end
+ else
+ case (state)
+ `ST_ON:
+ if (count == {16'b0,t_on})
+ begin
+ state <= `ST_SW;
+ count <= 32'b0;
+ end
+ else
+ count <= count + 32'b1;
+
+ `ST_SW:
+ if (count == {16'b0,t_sw})
+ begin
+ state <= `ST_LOOK;
+ count <= 32'b0;
+ end
+ else
+ count <= count + 24'b1;
+
+ `ST_LOOK:
+ if (count == {16'b0,t_look})
+ begin
+ state <= `ST_IDLE;
+ count <= 32'b0;
+ end
+ else
+ count <= count + 32'b1;
+
+ `ST_IDLE:
+ if (count == t_idle)
+ begin
+ state <= `ST_ON;
+ count <= 24'b0;
+ end
+ else
+ count <= count + 32'b1;
+
+ default: // Invalid state, reset state machine
+ begin
+ state <= `ST_ON;
+ count <= 32'b0;
+ end
+ endcase
+
+ assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz
+ assign tx_ctrl_o = (state == `ST_ON);
+ assign rx_ctrl_o = (state == `ST_LOOK);