+ if (o.reset)
+ stlink_reset(sl);
+
+ // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013
+ if (sl->chip_id == STM32_CHIPID_F4)
+ {
+ memset(sl->q_buf,0,4);
+ for (int i=0;i<8;i++) {
+ stlink_write_mem32(sl,0x40026000+0x10+0x18*i,4);
+ stlink_write_mem32(sl,0x40026400+0x10+0x18*i,4);
+ stlink_write_mem32(sl,0x40026000+0x24+0x18*i,4);
+ stlink_write_mem32(sl,0x40026400+0x24+0x18*i,4);
+ }
+ }
+ if (o.cmd == DO_WRITE) /* write */
+ {
+ if ((o.addr >= sl->flash_base) &&
+ (o.addr < sl->flash_base + sl->flash_size)) {
+ err = stlink_fwrite_flash(sl, o.filename, o.addr);
+ if (err == -1)
+ {
+ printf("stlink_fwrite_flash() == -1\n");
+ goto on_error;
+ }
+ }
+ else if ((o.addr >= sl->sram_base) &&
+ (o.addr < sl->sram_base + sl->sram_size)) {
+ err = stlink_fwrite_sram(sl, o.filename, o.addr);
+ if (err == -1)
+ {
+ printf("stlink_sram_flash() == -1\n");
+ goto on_error;
+ }
+ }
+ } else if (o.cmd == DO_ERASE)
+ {
+ err = stlink_erase_flash_mass(sl);
+ if (err == -1)
+ {
+ printf("stlink_fwrite_flash() == -1\n");
+ goto on_error;
+ }
+ }
+ else /* read */
+ {
+ if ((o.addr >= sl->flash_base) && (o.size == 0) &&
+ (o.addr < sl->flash_base + sl->flash_size))
+ o.size = sl->flash_size;
+ else if ((o.addr >= sl->sram_base) && (o.size == 0) &&
+ (o.addr < sl->sram_base + sl->sram_size))
+ o.size = sl->sram_size;
+ err = stlink_fread(sl, o.filename, o.addr, o.size);
+ if (err == -1)
+ {
+ printf("stlink_fread() == -1\n");
+ goto on_error;
+ }
+ }
+
+ if (o.reset)
+ stlink_reset(sl);
+
+ /* success */
+ err = 0;
+
+on_error:
+ if (sl != NULL)
+ {
+ stlink_exit_debug_mode(sl);
+ stlink_close(sl);
+ }