-sfr at (Z180_IO_BASE+0x20) SAR0L ; /* DMA source address reg, channel 0L */
-sfr at (Z180_IO_BASE+0x21) SAR0H ; /* DMA source address reg, channel 0H */
-sfr at (Z180_IO_BASE+0x22) SAR0B ; /* DMA source address reg, channel 0B */
-sfr at (Z180_IO_BASE+0x23) DAR0L ; /* DMA dest address reg, channel 0L */
-sfr at (Z180_IO_BASE+0x24) DAR0H ; /* DMA dest address reg, channel 0H */
-sfr at (Z180_IO_BASE+0x25) DAR0B ; /* DMA dest address reg, channel 0B */
-sfr at (Z180_IO_BASE+0x26) BCR0L ; /* DMA byte count reg, channel 0L */
-sfr at (Z180_IO_BASE+0x27) BCR0H ; /* DMA byte count reg, channel 0H */
-sfr at (Z180_IO_BASE+0x28) MAR1L ; /* DMA memory address reg, channel 1L */
-sfr at (Z180_IO_BASE+0x29) MAR1H ; /* DMA memory address reg, channel 1H */
-sfr at (Z180_IO_BASE+0x2A) MAR1B ; /* DMA memory address reg, channel 1B */
-sfr at (Z180_IO_BASE+0x2B) IAR1L ; /* DMA I/O address reg, channel 1L */
-sfr at (Z180_IO_BASE+0x2C) IAR1H ; /* DMA I/O address reg, channel 1H */
-sfr at (Z180_IO_BASE+0x2E) BCR1L ; /* DMA byte count reg, channel 1L */
-sfr at (Z180_IO_BASE+0x2F) BCR1H ; /* DMA byte count reg, channel 1H */
-sfr at (Z180_IO_BASE+0x30) DSTAT ; /* DMA status register */
-sfr at (Z180_IO_BASE+0x31) DMODE ; /* DMA mode register */
-sfr at (Z180_IO_BASE+0x32) DCNTL ; /* DMA/WAIT control register */
+__sfr __at (Z180_IO_BASE+0x20) SAR0L ; /* DMA source address reg, channel 0L */
+__sfr __at (Z180_IO_BASE+0x21) SAR0H ; /* DMA source address reg, channel 0H */
+__sfr __at (Z180_IO_BASE+0x22) SAR0B ; /* DMA source address reg, channel 0B */
+__sfr __at (Z180_IO_BASE+0x23) DAR0L ; /* DMA dest address reg, channel 0L */
+__sfr __at (Z180_IO_BASE+0x24) DAR0H ; /* DMA dest address reg, channel 0H */
+__sfr __at (Z180_IO_BASE+0x25) DAR0B ; /* DMA dest address reg, channel 0B */
+__sfr __at (Z180_IO_BASE+0x26) BCR0L ; /* DMA byte count reg, channel 0L */
+__sfr __at (Z180_IO_BASE+0x27) BCR0H ; /* DMA byte count reg, channel 0H */
+__sfr __at (Z180_IO_BASE+0x28) MAR1L ; /* DMA memory address reg, channel 1L */
+__sfr __at (Z180_IO_BASE+0x29) MAR1H ; /* DMA memory address reg, channel 1H */
+__sfr __at (Z180_IO_BASE+0x2A) MAR1B ; /* DMA memory address reg, channel 1B */
+__sfr __at (Z180_IO_BASE+0x2B) IAR1L ; /* DMA I/O address reg, channel 1L */
+__sfr __at (Z180_IO_BASE+0x2C) IAR1H ; /* DMA I/O address reg, channel 1H */
+__sfr __at (Z180_IO_BASE+0x2E) BCR1L ; /* DMA byte count reg, channel 1L */
+__sfr __at (Z180_IO_BASE+0x2F) BCR1H ; /* DMA byte count reg, channel 1H */
+__sfr __at (Z180_IO_BASE+0x30) DSTAT ; /* DMA status register */
+__sfr __at (Z180_IO_BASE+0x31) DMODE ; /* DMA mode register */
+__sfr __at (Z180_IO_BASE+0x32) DCNTL ; /* DMA/WAIT control register */