+#if defined(__SDCC_ADC_STYLE2455) || defined(__SDCC_ADC_STYLE97J60)
+
+// 97j60 family has 2 more possible ADC configs
+#if defined(__SDCC_ADC_STYLE97J60) // 97j60 family has 2 more ADC ports
+#define ADC_CFG_16A_0R 0x00
+#define ADC_CFG_16A_1R 0x10
+#define ADC_CFG_16A_2R 0x30
+#define ADC_CFG_15A_0R 0x00 // can switch only from 14 analog ports to 16 enabled analog ports
+#define ADC_CFG_15A_1R 0x10
+#define ADC_CFG_15A_2R 0x30
+#define ADC_CFG_14A_0R 0x01
+#define ADC_CFG_14A_1R 0x11
+#define ADC_CFG_14A_2R 0x31
+#define ADC_CFG_13A_0R 0x02
+#define ADC_CFG_13A_1R 0x12
+#define ADC_CFG_13A_2R 0x32
+#else
+#define ADC_CFG_13A_0R 0x01
+#define ADC_CFG_13A_1R 0x11
+#define ADC_CFG_13A_2R 0x31
+#endif
+#define ADC_CFG_12A_0R 0x03
+#define ADC_CFG_12A_1R 0x13
+#define ADC_CFG_12A_2R 0x33
+#define ADC_CFG_11A_0R 0x04
+#define ADC_CFG_11A_1R 0x14
+#define ADC_CFG_11A_2R 0x34
+#define ADC_CFG_10A_0R 0x05
+#define ADC_CFG_10A_1R 0x15
+#define ADC_CFG_10A_2R 0x35
+#define ADC_CFG_09A_0R 0x06
+#define ADC_CFG_09A_1R 0x16
+#define ADC_CFG_09A_2R 0x36
+#define ADC_CFG_08A_0R 0x07
+#define ADC_CFG_08A_1R 0x17
+#define ADC_CFG_08A_2R 0x37
+#define ADC_CFG_07A_0R 0x08
+#define ADC_CFG_07A_1R 0x18
+#define ADC_CFG_07A_2R 0x38
+#define ADC_CFG_06A_0R 0x09
+#define ADC_CFG_06A_1R 0x19
+#define ADC_CFG_06A_2R 0x39
+#define ADC_CFG_05A_0R 0x0a
+#define ADC_CFG_05A_1R 0x1a
+#define ADC_CFG_05A_2R 0x3a
+#define ADC_CFG_04A_0R 0x0b
+#define ADC_CFG_04A_1R 0x1b
+#define ADC_CFG_04A_2R 0x3b
+#define ADC_CFG_03A_0R 0x0c
+#define ADC_CFG_03A_1R 0x1c
+#define ADC_CFG_03A_2R 0x3c
+#define ADC_CFG_02A_0R 0x0d
+#define ADC_CFG_02A_1R 0x1d
+#define ADC_CFG_02A_2R 0x3d
+#define ADC_CFG_01A_0R 0x0e
+#define ADC_CFG_01A_1R 0x1e
+#define ADC_CFG_01A_2R 0x3e
+#define ADC_CFG_00A_0R 0x0f
+
+#else /* all other devices */
+