-/*
-
-Small Device C Compiler (SDCC) - PIC16F877 Device Library Header 2004
-
-Note an alterative header file can be generated from
-inc files using peal script support/scripts/inc2h.pl
-
-*/
-
-#ifndef PIC16F877_H
-#define PIC16F877_H
-
-
-/*****************************************************************************
- RAM
- *****************************************************************************/
-
-#pragma maxram 0x1FF
-
-#pragma memmap 0x0020 0x006f RAM 0x000
-#pragma memmap 0x0070 0x007f RAM 0x180
-#pragma memmap 0x00a0 0x00ef RAM 0x000
-#pragma memmap 0x0110 0x016f RAM 0x000
-#pragma memmap 0x0190 0x01ef RAM 0x000
-
-
-/*****************************************************************************
- Special Function Register Addresses
- *****************************************************************************/
-
-enum {
- indf_addr = 0x0000,
- tmr0_addr = 0x0001,
- pcl_addr = 0x0002,
- status_addr = 0x0003,
- fsr_addr = 0x0004,
- porta_addr = 0x0005,
- portb_addr = 0x0006,
- portc_addr = 0x0007,
- portd_addr = 0x0008,
- porte_addr = 0x0009,
- pclath_addr = 0x000a,
- intcon_addr = 0x000b,
- pir1_addr = 0x000c,
- pir2_addr = 0x000d,
- tmr1l_addr = 0x000e,
- tmr1h_addr = 0x000f,
- t1con_addr = 0x0010,
- tmr2_addr = 0x0011,
- t2con_addr = 0x0012,
- sspbuf_addr = 0x0013,
- sspcon_addr = 0x0014,
- ccpr1l_addr = 0x0015,
- ccpr1h_addr = 0x0016,
- ccp1con_addr = 0x0017,
- rcsta_addr = 0x0018,
- txreg_addr = 0x0019,
- rcreg_addr = 0x001a,
- ccpr2l_addr = 0x001b,
- ccpr2h_addr = 0x001c,
- ccp2con_addr = 0x001d,
- adresh_addr = 0x001e,
- adcon0_addr = 0x001f,
- option_reg_addr = 0x0081,
- trisa_addr = 0x0085,
- trisb_addr = 0x0086,
- trisc_addr = 0x0087,
- trisd_addr = 0x0088,
- trise_addr = 0x0089,
- pie1_addr = 0x008c,
- pie2_addr = 0x008d,
- pcon_addr = 0x008e,
- sspcon2_addr = 0x0091,
- pr2_addr = 0x0092,
- sspadd_addr = 0x0093,
- sspstat_addr = 0x0094,
- txsta_addr = 0x0098,
- spbrg_addr = 0x0099,
- adresl_addr = 0x009e,
- adcon1_addr = 0x009f,
- eedata_addr = 0x010c,
- eeadr_addr = 0x010d,
- eedath_addr = 0x010e,
- eeadrh_addr = 0x010f,
- eecon1_addr = 0x018c,
- eecon2_addr = 0x018d,
- config_addr = 0x2007
-};
-
-/* Special function register memory map - memmap start_addr end_addr type bank_mask */
-#pragma memmap 0x001 0x001 SFR 0x080
-#pragma memmap 0x002 0x004 SFR 0x180
-#pragma memmap 0x005 0x005 SFR 0x000
-#pragma memmap 0x006 0x006 SFR 0x080
-#pragma memmap 0x007 0x009 SFR 0x000
-#pragma memmap 0x00a 0x00b SFR 0x180
-#pragma memmap 0x00c 0x01f SFR 0x000
-#pragma memmap 0x081 0x081 SFR 0x100
-#pragma memmap 0x085 0x085 SFR 0x000
-#pragma memmap 0x086 0x086 SFR 0x100
-#pragma memmap 0x087 0x089 SFR 0x000
-#pragma memmap 0x08c 0x08e SFR 0x000
-#pragma memmap 0x091 0x094 SFR 0x000
-#pragma memmap 0x098 0x099 SFR 0x000
-#pragma memmap 0x09c 0x09f SFR 0x000
-#pragma memmap 0x10c 0x10f SFR 0x000
-#pragma memmap 0x18c 0x18d SFR 0x000
-
-
-/*****************************************************************************
- Misc Registers
- *****************************************************************************/
-
-/* ---- STATUS Bits -------------------------------------------------------- */
+//
+// Register Declarations for Microchip 16F877 Processor
+//
+//
+// This header file was automatically generated by:
+//
+// inc2h.pl V4783
+//
+// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+//
+// SDCC is licensed under the GNU Public license (GPL) v2. Note that
+// this license covers the code to the compiler and other executables,
+// but explicitly does not cover any code or objects generated by sdcc.
+// We have not yet decided on a license for the run time libraries, but
+// it will not put any requirements on code linked against it. See:
+//
+// http://www.gnu.org/copyleft/gpl/html
+//
+// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
+//
+//
+#ifndef P16F877_H
+#define P16F877_H
+
+//
+// Register addresses.
+//
+#define INDF_ADDR 0x0000
+#define TMR0_ADDR 0x0001
+#define PCL_ADDR 0x0002
+#define STATUS_ADDR 0x0003
+#define FSR_ADDR 0x0004
+#define PORTA_ADDR 0x0005
+#define PORTB_ADDR 0x0006
+#define PORTC_ADDR 0x0007
+#define PORTD_ADDR 0x0008
+#define PORTE_ADDR 0x0009
+#define PCLATH_ADDR 0x000A
+#define INTCON_ADDR 0x000B
+#define PIR1_ADDR 0x000C
+#define PIR2_ADDR 0x000D
+#define TMR1L_ADDR 0x000E
+#define TMR1H_ADDR 0x000F
+#define T1CON_ADDR 0x0010
+#define TMR2_ADDR 0x0011
+#define T2CON_ADDR 0x0012
+#define SSPBUF_ADDR 0x0013
+#define SSPCON_ADDR 0x0014
+#define CCPR1L_ADDR 0x0015
+#define CCPR1H_ADDR 0x0016
+#define CCP1CON_ADDR 0x0017
+#define RCSTA_ADDR 0x0018
+#define TXREG_ADDR 0x0019
+#define RCREG_ADDR 0x001A
+#define CCPR2L_ADDR 0x001B
+#define CCPR2H_ADDR 0x001C
+#define CCP2CON_ADDR 0x001D
+#define ADRESH_ADDR 0x001E
+#define ADCON0_ADDR 0x001F
+#define OPTION_REG_ADDR 0x0081
+#define TRISA_ADDR 0x0085
+#define TRISB_ADDR 0x0086
+#define TRISC_ADDR 0x0087
+#define TRISD_ADDR 0x0088
+#define TRISE_ADDR 0x0089
+#define PIE1_ADDR 0x008C
+#define PIE2_ADDR 0x008D
+#define PCON_ADDR 0x008E
+#define SSPCON2_ADDR 0x0091
+#define PR2_ADDR 0x0092
+#define SSPADD_ADDR 0x0093
+#define SSPSTAT_ADDR 0x0094
+#define TXSTA_ADDR 0x0098
+#define SPBRG_ADDR 0x0099
+#define ADRESL_ADDR 0x009E
+#define ADCON1_ADDR 0x009F
+#define EEDATA_ADDR 0x010C
+#define EEADR_ADDR 0x010D
+#define EEDATH_ADDR 0x010E
+#define EEADRH_ADDR 0x010F
+#define EECON1_ADDR 0x018C
+#define EECON2_ADDR 0x018D
+
+//
+// Memory organization.
+//
+
+
+
+// LIST
+// P16F877.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
+// NOLIST
+
+// This header file defines configurations, registers, and other useful bits of
+// information for the PIC16F877 microcontroller. These names are taken to match
+// the data sheets as closely as possible.
+
+// Note that the processor must be selected before this file is
+// included. The processor may be selected the following ways:
+
+// 1. Command line switch:
+// C:\ MPASM MYFILE.ASM /PIC16F877
+// 2. LIST directive in the source file
+// LIST P=PIC16F877
+// 3. Processor Type entry in the MPASM full-screen interface
+
+//==========================================================================
+//
+// Revision History
+//
+//==========================================================================
+
+//Rev: Date: Reason:
+
+//1.12 01/12/00 Changed some bit names, a register name, configuration bits
+// to match datasheet (DS30292B)
+//1.00 08/07/98 Initial Release
+
+//==========================================================================
+//
+// Verify Processor
+//
+//==========================================================================
+
+// IFNDEF __16F877
+// MESSG "Processor-header file mismatch. Verify selected processor."
+// ENDIF
+
+//==========================================================================
+//
+// Register Definitions
+//
+//==========================================================================
+
+#define W 0x0000
+#define F 0x0001
+
+//----- Register Files------------------------------------------------------
+
+extern __sfr __at (INDF_ADDR) INDF;
+extern __sfr __at (TMR0_ADDR) TMR0;
+extern __sfr __at (PCL_ADDR) PCL;
+extern __sfr __at (STATUS_ADDR) STATUS;
+extern __sfr __at (FSR_ADDR) FSR;
+extern __sfr __at (PORTA_ADDR) PORTA;
+extern __sfr __at (PORTB_ADDR) PORTB;
+extern __sfr __at (PORTC_ADDR) PORTC;
+extern __sfr __at (PORTD_ADDR) PORTD;
+extern __sfr __at (PORTE_ADDR) PORTE;
+extern __sfr __at (PCLATH_ADDR) PCLATH;
+extern __sfr __at (INTCON_ADDR) INTCON;
+extern __sfr __at (PIR1_ADDR) PIR1;
+extern __sfr __at (PIR2_ADDR) PIR2;
+extern __sfr __at (TMR1L_ADDR) TMR1L;
+extern __sfr __at (TMR1H_ADDR) TMR1H;
+extern __sfr __at (T1CON_ADDR) T1CON;
+extern __sfr __at (TMR2_ADDR) TMR2;
+extern __sfr __at (T2CON_ADDR) T2CON;
+extern __sfr __at (SSPBUF_ADDR) SSPBUF;
+extern __sfr __at (SSPCON_ADDR) SSPCON;
+extern __sfr __at (CCPR1L_ADDR) CCPR1L;
+extern __sfr __at (CCPR1H_ADDR) CCPR1H;
+extern __sfr __at (CCP1CON_ADDR) CCP1CON;
+extern __sfr __at (RCSTA_ADDR) RCSTA;
+extern __sfr __at (TXREG_ADDR) TXREG;
+extern __sfr __at (RCREG_ADDR) RCREG;
+extern __sfr __at (CCPR2L_ADDR) CCPR2L;
+extern __sfr __at (CCPR2H_ADDR) CCPR2H;
+extern __sfr __at (CCP2CON_ADDR) CCP2CON;
+extern __sfr __at (ADRESH_ADDR) ADRESH;
+extern __sfr __at (ADCON0_ADDR) ADCON0;
+
+extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
+extern __sfr __at (TRISA_ADDR) TRISA;
+extern __sfr __at (TRISB_ADDR) TRISB;
+extern __sfr __at (TRISC_ADDR) TRISC;
+extern __sfr __at (TRISD_ADDR) TRISD;
+extern __sfr __at (TRISE_ADDR) TRISE;
+extern __sfr __at (PIE1_ADDR) PIE1;
+extern __sfr __at (PIE2_ADDR) PIE2;
+extern __sfr __at (PCON_ADDR) PCON;
+extern __sfr __at (SSPCON2_ADDR) SSPCON2;
+extern __sfr __at (PR2_ADDR) PR2;
+extern __sfr __at (SSPADD_ADDR) SSPADD;
+extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
+extern __sfr __at (TXSTA_ADDR) TXSTA;
+extern __sfr __at (SPBRG_ADDR) SPBRG;
+extern __sfr __at (ADRESL_ADDR) ADRESL;
+extern __sfr __at (ADCON1_ADDR) ADCON1;
+
+extern __sfr __at (EEDATA_ADDR) EEDATA;
+extern __sfr __at (EEADR_ADDR) EEADR;
+extern __sfr __at (EEDATH_ADDR) EEDATH;
+extern __sfr __at (EEADRH_ADDR) EEADRH;
+
+extern __sfr __at (EECON1_ADDR) EECON1;
+extern __sfr __at (EECON2_ADDR) EECON2;
+
+//----- STATUS Bits --------------------------------------------------------
+
+
+//----- INTCON Bits --------------------------------------------------------
+
+
+//----- PIR1 Bits ----------------------------------------------------------
+
+
+//----- PIR2 Bits ----------------------------------------------------------
+
+
+//----- T1CON Bits ---------------------------------------------------------
+
+
+//----- T2CON Bits ---------------------------------------------------------
+
+
+//----- SSPCON Bits --------------------------------------------------------
+
+
+//----- CCP1CON Bits -------------------------------------------------------
+
+
+//----- RCSTA Bits ---------------------------------------------------------
+
+
+//----- CCP2CON Bits -------------------------------------------------------
+
+
+//----- ADCON0 Bits --------------------------------------------------------
+
+
+//----- OPTION_REG Bits -----------------------------------------------------
+
+
+//----- TRISE Bits ---------------------------------------------------------
+
+
+//----- PIE1 Bits ----------------------------------------------------------
+
+
+//----- PIE2 Bits ----------------------------------------------------------
+
+
+//----- PCON Bits ----------------------------------------------------------
+
+
+//----- SSPCON2 Bits --------------------------------------------------------
+
+
+//----- SSPSTAT Bits -------------------------------------------------------
+
+
+//----- TXSTA Bits ---------------------------------------------------------
+
+
+//----- ADCON1 Bits --------------------------------------------------------
+
+
+//----- EECON1 Bits --------------------------------------------------------
+
+
+//==========================================================================
+//
+// RAM Definition
+//
+//==========================================================================
+
+// __MAXRAM H'1FF'
+// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D'
+// __BADRAM H'105', H'107'-H'109'
+// __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
+
+//==========================================================================
+//
+// Configuration Bits
+//
+//==========================================================================
+
+#define _CP_ALL 0x0FCF
+#define _CP_HALF 0x1FDF
+#define _CP_UPPER_256 0x2FEF
+#define _CP_OFF 0x3FFF
+#define _DEBUG_ON 0x37FF
+#define _DEBUG_OFF 0x3FFF
+#define _WRT_ENABLE_ON 0x3FFF
+#define _WRT_ENABLE_OFF 0x3DFF
+#define _CPD_ON 0x3EFF
+#define _CPD_OFF 0x3FFF
+#define _LVP_ON 0x3FFF
+#define _LVP_OFF 0x3F7F
+#define _BODEN_ON 0x3FFF
+#define _BODEN_OFF 0x3FBF
+#define _PWRTE_OFF 0x3FFF
+#define _PWRTE_ON 0x3FF7
+#define _WDT_ON 0x3FFF
+#define _WDT_OFF 0x3FFB
+#define _LP_OSC 0x3FFC
+#define _XT_OSC 0x3FFD
+#define _HS_OSC 0x3FFE
+#define _RC_OSC 0x3FFF
+
+// LIST
+
+// ----- ADCON0 bits --------------------