- Ports P0 & P2 are not available for the programmer if external ROM used.
- Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0 & P2.
+ Ports P0 & P2 are not available if external ROM used.
+ Use statement "#define MCS51REG_EXTERNAL_ROM" to undefine P0 & P2.
- Ports P0, P2, P3_6, WR, P3_7 & RD are not available for the programmer if
- external RAM is used.
+ Ports P0, P2, P3_6, WR, P3_7 & RD are not available if external RAM is used.
-#define CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0
-#define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
+#define CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
+#define CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
#endif
#ifdef ADCON1
#undef ADCON1
sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
// Not directly accessible ADCON1
#endif
#ifdef ADCON1
#undef ADCON1
sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
// Not directly accessible ADCON1
#endif
#ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
#undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
#endif
#ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
#undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
-#define AADR0 0x01
-#define AADR1 0x02
-#define AADR2 0x04
-#define ADCS 0x08
-#define ADCI 0x10
-#define ADEX 0x20
-#define ADC_0 0x40 // different name as ADC0 in P5
-#define ADC_1 0x80 // different name as ADC1 in P5
+#define AADR0 0x01
+#define AADR1 0x02
+#define AADR2 0x04
+#define ADCS 0x08
+#define ADCI 0x10
+#define ADEX 0x20
+#define ADC_0 0x40 // different name as ADC0 in P5
+#define ADC_1 0x80 // different name as ADC1 in P5
-#ifdef CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0
-#undef CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0
-sfr at 0xD8 CCON; // T89C51RD2 specific register
+#ifdef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
+#undef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
+sfr at 0xD8 CCON ; // T89C51RD2 specific register
#endif
#ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
#undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
// Not directly accessible Bits.
#endif
#ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
#undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
// Not directly accessible Bits.
#endif
#ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
#undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
#endif
#ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
#undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
-#ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
-#undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
-sfr at 0xD9 CMOD;
-#define ECF 0x01
-#define CPS0 0x02
-#define CPS1 0x04
-#define WDTE 0x40
-#define CIDL 0x80
+#ifdef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
+#undef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
+sfr at 0xD9 CMOD ;
+#define ECF 0x01
+#define CPS0 0x02
+#define CPS1 0x04
+#define WDTE 0x40
+#define CIDL 0x80
#endif
#ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
#undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
#endif
#ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
#undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
#endif
#ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
#undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
#endif
#ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
#undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
#endif
#ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
#undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
#endif
#ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
#undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
#endif
#ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
#undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
#endif
#ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
#undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
#endif
#ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
#undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
#endif
#ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
#undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
#endif
#ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
#undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
#endif
#ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
#undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
#endif
#ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
#undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
#endif
#ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
#undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
#endif
#ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
#undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
#endif
#ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
#undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
#endif
#ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
#undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
#endif
#ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
#undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
-sbit at 0xA8 EX0 ;
-sbit at 0xA9 ET0 ;
-sbit at 0xAA EX1 ;
-sbit at 0xAB ET1 ;
-sbit at 0xAC ES ;
-sbit at 0xAC ES0 ;
-sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
-sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
-sbit at 0xAF EA ;
-sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
+sbit at 0xA8 EX0 ;
+sbit at 0xA9 ET0 ;
+sbit at 0xAA EX1 ;
+sbit at 0xAB ET1 ;
+sbit at 0xAC ES ;
+sbit at 0xAC ES0 ;
+sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
+sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
+sbit at 0xAF EA ;
+sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
#ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
#undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
#ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
#undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
-sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific
-sfr at 0xB8 IP0 ; // alternate name
+sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific
+sfr at 0xB8 IP0 ; // alternate name
#endif
#ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
#undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
#endif
#ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
#undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
#endif
#ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
#undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
#endif
#ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
#undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
#endif
#ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
#undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
#endif
#ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
#undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
#endif
#ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
#undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
#endif
#ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
#undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
#endif
#ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
#undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
#endif
#ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
#undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
#endif
#ifdef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
#undef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
#endif
#ifdef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
#undef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
// Bit registers
sbit at 0xC0 IADC ; // A/D converter irq flag
sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
// Bit registers
sbit at 0xC0 IADC ; // A/D converter irq flag
sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
#endif
#ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
#undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
sfr at 0xC6 MCON ; // DS80C390
#endif
#ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
#undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
sfr at 0xC6 MCON ; // DS80C390
#endif
#ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
#undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
sfr at 0xC6 MCON ; // DS5000
#endif
#ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
#undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
sfr at 0xC6 MCON ; // DS5000
#endif
#ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
#undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
sfr at 0xC6 MCON ; // DS5001
#endif
#ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
#undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
sfr at 0xC6 MCON ; // DS5001
#endif
#ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
#undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
// P1 alternate functions
#endif
#ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
#undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
// P1 alternate functions
#ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
#undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
// Bit registers
#ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
#undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
// Bit registers
#ifdef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
#undef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
#ifdef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
#undef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
#endif
#ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
#undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
#endif
#ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
#undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
#endif
#ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
#undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
#endif
#ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
#undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
#endif
#ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
#undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
#endif
#ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
#undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
#endif
#ifdef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
#undef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
#endif
#ifdef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
#undef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
#endif
#ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
#undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
#endif
#ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
#undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
#endif
#ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
#undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
#endif
#ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
#undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
#endif
#ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
#undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
#endif
#ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
#undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
#endif
#ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
#undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
#endif
#ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
#undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
#endif
#ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
#undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
#endif
#ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
#undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
#endif
#ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
#undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
#endif
#ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
#undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
#endif
#ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
#undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
#endif
#ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
#undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
#ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
#undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
// serial channel 0 buffer register SAB80517 specific(same as stock SCON)
#ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
#undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
// serial channel 0 buffer register SAB80517 specific(same as stock SCON)
#endif
#ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
#undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
#endif
#ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
#undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
-sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific
-sfr at 0xD8 SICON ; // sometimes called SICON
+sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific
+sfr at 0xD8 SICON ; // sometimes called SICON
-sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific
-sfr at 0xDA SIDAT ; // sometimes called SIDAT
+sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific
+sfr at 0xDA SIDAT ; // sometimes called SIDAT
#endif
#ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
#undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
#endif
#ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
#undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
#endif
#ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
#undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
#endif
#ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
#undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
#endif
#ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
#undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
#endif
#ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
#undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
#endif
#ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
#undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
#endif
#ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
#undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
#endif
#ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
#undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
#endif
#ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
#undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
#endif
#ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
#undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
#endif
#ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
#undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
-#define SYSCON_XMAP0 0x01
-#define SYSCON_XMAP1 0x02
-#define SYSCON_RMAP 0x10
-#define SYSCON_EALE 0x20
+#define SYSCON_XMAP0 0x01
+#define SYSCON_XMAP1 0x02
+#define SYSCON_RMAP 0x10
+#define SYSCON_EALE 0x20
#endif
#ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
#undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
#endif
#ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
#undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
#endif
#ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
#undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
#endif
#ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
#undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
#endif
#ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
#undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
// Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
#endif
#ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
#undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
// Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
#endif
#ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
#undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
// Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
#endif
#ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
#undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
// Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
#endif
#ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
#undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
#endif
#ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
#undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
#endif
#ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
#undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
#endif
#ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
#undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
-#define TF2_VECTOR 5 /* 0x2B */
-#define PFI_VECTOR 6 /* 0x33 */
-#define SIO1_VECTOR 7 /* 0x3B */
-#define IE2_VECTOR 8 /* 0x43 */
-#define IE3_VECTOR 9 /* 0x4B */
-#define IE4_VECTOR 10 /* 0x53 */
-#define IE5_VECTOR 11 /* 0x5B */
-#define WDI_VECTOR 12 /* 0x63 */
+#define TF2_VECTOR 5 /* 0x2B */
+#define PFI_VECTOR 6 /* 0x33 */
+#define SIO1_VECTOR 7 /* 0x3B */
+#define IE2_VECTOR 8 /* 0x43 */
+#define IE3_VECTOR 9 /* 0x4B */
+#define IE4_VECTOR 10 /* 0x53 */
+#define IE5_VECTOR 11 /* 0x5B */
+#define WDI_VECTOR 12 /* 0x63 */
-#define TF2_VECTOR 5 /* 0x2B */
-#define PFI_VECTOR 6 /* 0x33 */
-#define SIO1_VECTOR 7 /* 0x3B */
-#define IE2_VECTOR 8 /* 0x43 */
-#define IE3_VECTOR 9 /* 0x4B */
-#define IE4_VECTOR 10 /* 0x53 */
-#define IE5_VECTOR 11 /* 0x5B */
-#define WDI_VECTOR 12 /* 0x63 */
+#define TF2_VECTOR 5 /* 0x2B */
+#define PFI_VECTOR 6 /* 0x33 */
+#define SIO1_VECTOR 7 /* 0x3B */
+#define IE2_VECTOR 8 /* 0x43 */
+#define IE3_VECTOR 9 /* 0x4B */
+#define IE4_VECTOR 10 /* 0x53 */
+#define IE5_VECTOR 11 /* 0x5B */
+#define WDI_VECTOR 12 /* 0x63 */
-#define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
-#define CT0_VECTOR 6 // 0x33 T2 capture 0
-#define CT1_VECTOR 7 // 0x3B T2 capture 1
-#define CT2_VECTOR 8 // 0x43 T2 capture 2
-#define CT3_VECTOR 9 // 0x4B T2 capture 3
-#define ADC_VECTOR 10 // 0x53 ADC completion
-#define CM0_VECTOR 11 // 0x5B T2 compare 0
-#define CM1_VECTOR 12 // 0x63 T2 compare 1
-#define CM2_VECTOR 13 // 0x6B T2 compare 2
-#define TF2_VECTOR 14 // 0x73 T2 overflow
+#define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
+#define CT0_VECTOR 6 // 0x33 T2 capture 0
+#define CT1_VECTOR 7 // 0x3B T2 capture 1
+#define CT2_VECTOR 8 // 0x43 T2 capture 2
+#define CT3_VECTOR 9 // 0x4B T2 capture 3
+#define ADC_VECTOR 10 // 0x53 ADC completion
+#define CM0_VECTOR 11 // 0x5B T2 compare 0
+#define CM1_VECTOR 12 // 0x63 T2 compare 1
+#define CM2_VECTOR 13 // 0x6B T2 compare 2
+#define TF2_VECTOR 14 // 0x73 T2 overflow
-#define SIO1_VECTOR 5 // 0x2b SIO1 (i2c)
-#define PCA_VECTOR 6 // 0x33 (Programmable Counter Array)
-#define TF2_VECTOR 7 // 0x3B (Timer 2)
+#define SIO1_VECTOR 5 // 0x2b SIO1 (i2c)
+#define PCA_VECTOR 6 // 0x33 (Programmable Counter Array)
+#define TF2_VECTOR 7 // 0x3B (Timer 2)
-#define TF2_VECTOR 5 /* 0x2B timer 2 */
-#define PCA_VECTOR 6 /* 0x33 Programmable Counter Array interrupt */
+#define TF2_VECTOR 5 /* 0x2B timer 2 */
+#define PCA_VECTOR 6 /* 0x33 Programmable Counter Array interrupt */