- those header pins are VCC?
- pin 37, 35 is VCCIO
- pin 24 is TMS
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- WTF?
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- SOT-23 with G1 label could be:
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- transistor, 1=B, 2=E, 3(sole)=C
- fet, 1=G, 2=S, 3=D
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- so:
- TMS is driving base or gate
- 3.3V is on emitter or source
- header VCC is on collector or drain
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- TMS is 'test mode state' on the jtag interface, which drives the TAP
- controller state machine. TMS going low starts a cycle?
+ if it's an NPN transistor:
+ emitter attached to VCCINT
+ base and collector both to VCCIO
+ VCCIO is driven by 3.3V regulator, VCCINT is not