BTM-182 bluetooth module .. the latter should be budgeted at about $15 each
in quantity 100 .. uses async serial, less dev effort, no regulatory issues
+2011.03.31
+- Raysom BTM-182 peak current draw is 58mA, Roving Networks RN-42 peaks at 50mA
+
+ Raysom gave us a quote of $10 per delivered at q100
+
+ RovingNetworks replied to our quote request but we don't have a number yet
+
+ Rough estimate of cogs puts us at retail price of $150
+
+2011.04.13
+- Pondering how much to clip off the SMA end of the PCB to ensure the SMA
+ flange fits inside the box.
+
+ Our connector needs 3.81 mm "above" the PCB which for TeleBT actually
+ means between the PCB bottom surface and the base of the box. The box
+ boss height is specified as 4mm, so that fits in a purely vertical sense,
+ but I'm worried about the box wall to base radius, and the fact that the
+ box walls aren't exactly vertical.
+
+ Hammond doesn't specify the radius between the wall and base of the 1551K
+ box. Given other things they do specify, it might be that 1 mm is a
+ conservative guess. The specification for the inside dimensions of the lip
+ around the lid is 10 mils smaller than the max PCB dimensions, and it *looks*
+ like that inside edge might be about where the wall radius ends. The drawing
+ shows the lid inside as 6.73mm less than box outside dimension, which seems
+ reasonably consistent with my estimate of a 2mm wall thickness, about 1mm
+ for the lid lip, and some mold tolerances. So, let's use the box lid lip
+ inside dimensions as a proxy for the box base inside dimensions until proven
+ otherwise.
+
+ So we need to peel 5 mils off to account for the box radius. The flange
+ itself is 40 mils. And I'm nervous about the guesstimates so I'll add
+ another 5 mils of margin. So we need to take 50 mils off the SMA end of
+ the PCB.
+
+ As a sanity check, on TeleDongle the closes screw hole is 78 mils from the
+ SMA edge of the PCB, which is 50 mils less than a maximum-size PCB would
+ have. If anything, the TeleDongle SMA ends up inside the wall a bit more
+ that necessary, such that tightening the SMA nut deflects the wall inward.
+ So, 50 mils might indeed be a good choice for TeleBT. We'll give it a try!
+
+2011.06.07
+- as I start to work on rotating the design, noting the changes between the
+ max 1551 board outline and what I used for v0.1:
+
+ outline layer:
+
+ - Line[278543 24606 291339 24606 1000 2000 "lock"]
+ - Line[291339 24606 291339 129921 1000 2000 "lock"]
+ - Line[287402 133854 24606 133854 1000 2000 "lock"]
+ - Arc[287402 129921 3937 3937 1000 2000 90 90 "lock"]
+ + Line[278543 24606 286338 24606 1000 2000 "lock"]
+ + Line[286338 133854 24606 133854 1000 2000 "lock"]
+ + Line[286338 24606 286338 133854 1000 2000 "lock"]
+
+ similar changes on the top layer:
+
+ - Line[287402 133854 24606 133854 100 2000 "clearline,lock"]
+ - Line[24606 133854 24606 121063 100 2000 "clearline,lock"]
+ - Line[12795 109252 0 109252 100 2000 "clearline,lock"]
+ - Line[3927 0 266732 0 100 2000 "clearline,lock"]
+ - Line[291339 24606 291339 129921 100 2000 "clearline,lock"]
+ - Line[278543 24606 291339 24606 100 2000 "clearline,lock"]
+ - Line[266732 0 266732 12795 100 2000 "clearline,lock"]
+ - Line[0 109252 0 3937 100 2000 "clearline,lock"]
+ - Arc[3937 3937 3937 3937 100 2000 270 90 "clearline,lock"]
+ - Arc[278543 12795 11811 11811 100 2000 0 90 "clearline,lock"]
+ - Arc[287402 129921 3937 3937 100 2000 90 90 "clearline,lock"]
+ - Arc[12795 121063 11811 11811 100 2000 180 90 "clearline,lock"]
+ + Line[286338 24606 286338 133854 600 2000 "clearline,lock"]
+ + Line[286338 133854 24606 133854 600 2000 "clearline,lock"]
+ + Line[24606 133854 24606 121063 600 2000 "clearline,lock"]
+ + Line[12795 109252 0 109252 600 2000 "clearline,lock"]
+ + Line[3927 0 266732 0 600 2000 "clearline,lock"]
+ + Line[278543 24606 286338 24606 600 2000 "clearline,lock"]
+ + Line[266732 0 266732 12795 600 2000 "clearline,lock"]
+ + Line[0 109252 0 3937 600 2000 "clearline,lock"]
+ + Arc[3937 3937 3937 3937 600 2000 270 90 "clearline,lock"]
+ + Arc[278543 12795 11811 11811 600 2000 0 90 "clearline,lock"]
+ + Arc[12795 121063 11811 11811 600 2000 180 90 "clearline,lock"]
+
+2013.01.25
+- reviewing design with an eye towards moving to production
+
+ - we have the ability to sample v_lipo, but is it useful?
+
+- need to move design to current preferred parts list
+- verify button fits cleanly through box wall
+- artwork is solid .. did a lot for v0.3
+
+2013.04.08
+- problems in v1.0 build fixed for v1.1
+ + companion and debug connectors should be rotated so cable dresses
+ towards center of board like TD
+ + update D1 footprint to clearly indicate cathode end so we don't
+ mess that up again
+ + we're not loading the flash part, so just remove it
+
+2016.03.20
+- to build a TeleBT with BTle:
+ + swap out Rayson module for DK BM70BLES1FC2-0002AA-ND
+ ? swap out CPU for STM32F042, since it has in-built USB bootloader