00001 /* ---------------------------------------------------------------------- 00002 * Copyright (C) 2010 ARM Limited. All rights reserved. 00003 * 00004 * $Date: 15. July 2011 00005 * $Revision: V1.0.10 00006 * 00007 * Project: CMSIS DSP Library 00008 * Title: arm_biquad_cascade_df1_32x64_init_q31.c 00009 * 00010 * Description: High precision Q31 Biquad cascade filter initialization function. 00011 * 00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 00013 * 00014 * Version 1.0.10 2011/7/15 00015 * Big Endian support added and Merged M0 and M3/M4 Source code. 00016 * 00017 * Version 1.0.3 2010/11/29 00018 * Re-organized the CMSIS folders and updated documentation. 00019 * 00020 * Version 1.0.2 2010/11/11 00021 * Documentation updated. 00022 * 00023 * Version 1.0.1 2010/10/05 00024 * Production release and review comments incorporated. 00025 * 00026 * Version 1.0.0 2010/09/20 00027 * Production release and review comments incorporated. 00028 * 00029 * Version 0.0.7 2010/06/10 00030 * Misra-C changes done 00031 * -------------------------------------------------------------------- */ 00032 00033 #include "arm_math.h" 00034 00077 void arm_biquad_cas_df1_32x64_init_q31( 00078 arm_biquad_cas_df1_32x64_ins_q31 * S, 00079 uint8_t numStages, 00080 q31_t * pCoeffs, 00081 q63_t * pState, 00082 uint8_t postShift) 00083 { 00084 /* Assign filter stages */ 00085 S->numStages = numStages; 00086 00087 /* Assign postShift to be applied to the output */ 00088 S->postShift = postShift; 00089 00090 /* Assign coefficient pointer */ 00091 S->pCoeffs = pCoeffs; 00092 00093 /* Clear state buffer and size is always 4 * numStages */ 00094 memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t)); 00095 00096 /* Assign state pointer */ 00097 S->pState = pState; 00098 } 00099