     [file version.texi not included]

OpenOCD
*******

This manual documents edition EDITION of the Open On-Chip Debugger (OpenOCD) version VERSION, UPDATED.

Copyright © 2007-2008 Spen spen@spen-soft.co.uk

Copyright © 2008 Oyvind Harboe oyvind.harboe@zylin.com

     Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts.  A copy of the license is included in the section entitled ``GNU Free Documentation License''.

About
*****

The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming and boundary-scan testing for embedded target devices. The targets are interfaced using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other connection types in the future.

OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.

Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.

Developers
**********

OpenOCD was created by Dominic Rath as part of a diploma thesis written at the University of Applied Sciences Augsburg (http://www.fh-augsburg.de). Others interested in improving the state of free and open debug and testing technology are welcome to participate.

Other developers have contributed support for additional targets and flashes as well as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.

The main OpenOCD web site is available at http://openocd.berlios.de/web/

Building
********

If you are interested in getting actual work done rather than building OpenOCD, then check if your interface supplier provides binaries for you. Chances are that that binary is from some SVN version that is more stable than SVN trunk where bleeding edge development takes place.

You can download the current SVN version with SVN client of your choice from the following repositories:

(svn://svn.berlios.de/openocd/trunk)

or

(http://svn.berlios.de/svnroot/repos/openocd/trunk)

Using the SVN command line client, you can use the following command to fetch the latest version (make sure there is no (non-svn) directory called "openocd" in the current directory):

      svn checkout svn://svn.berlios.de/openocd/trunk openocd

Building OpenOCD requires a recent version of the GNU autotools. On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows, you have to use Cygwin. Make sure that your PATH environment variable contains no other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin paths, resulting in obscure dependency errors (This is an observation I've gathered from the logs of one user - correct me if I'm wrong).

You further need the appropriate driver files, if you want to build support for a FTDI FT2232 based interface:

  * ftdi2232 libftdi (http://www.intra2net.com/opensource/ftdi/)

  * ftd2xx libftd2xx (http://www.ftdichip.com/Drivers/D2XX.htm)

  * When using the Amontec JTAGkey, you have to get the drivers from the Amontec homepage (www.amontec.com), as the JTAGkey uses a non-standard VID/PID.

libftdi is supported under windows. Versions earlier than 0.13 will require patching. see contrib/libftdi for more details.

In general, the D2XX driver provides superior performance (several times as fast), but has the draw-back of being binary-only - though that isn't that bad, as it isn't a kernel module, only a user space library.

To build OpenOCD (on both Linux and Cygwin), use the following commands:

      ./bootstrap

Bootstrap generates the configure script, and prepares building on your system.

      ./configure

Configure generates the Makefiles used to build OpenOCD.

      make

Make builds OpenOCD, and places the final executable in ./src/.

The configure script takes several options, specifying which JTAG interfaces should be included:

  * --enable-parport

  * --enable-parport_ppdev

  * --enable-parport_giveio

  * --enable-amtjtagaccel

  * --enable-ft2232_ftd2xx (Using the latest D2XX drivers from FTDI and following their installation instructions, I had to use --enable-ft2232_libftd2xx for OpenOCD to build properly.)

  * --enable-ft2232_libftdi

  * --with-ftd2xx=/path/to/d2xx/

  * --enable-gw16012

  * --enable-usbprog

  * --enable-presto_libftdi

  * --enable-presto_ftd2xx

  * --enable-jlink

If you want to access the parallel port using the PPDEV interface you have to specify both the --enable-parport AND the --enable-parport_ppdev option since the --enable-parport_ppdev option actually is an option to the parport driver (see http://forum.sparkfun.com/viewtopic.php?t=3795 for more info).

Cygwin users have to specify the location of the FTDI D2XX package. This should be an absolute path containing no spaces.

Linux users should copy the various parts of the D2XX package to the appropriate locations, i.e. /usr/include, /usr/lib.

Miscellaneous configure options

  * --enable-gccwarnings - enable extra gcc warnings during build

Running
*******

OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other). Run with --help or -h to view the available command line switches.

It reads its configuration by default from the file openocd.cfg located in the current working directory. This may be overwritten with the -f <configfile> command line switch.  The -f command line switch can be specified multiple times, in which case the config files are executed in order.

Also it is possible to interleave commands w/config scripts using the -c command line switch.

To enable debug output (when reporting problems or working on OpenOCD itself), use the -d command line switch. This sets the debug_level to "3", outputting the most information, including debug messages. The default setting is "2", outputting only informational messages, warnings and errors. You can also change this setting from within a telnet or gdb session using debug_level <n> See debug_level.

You can redirect all output from the daemon to a file using the -l <logfile> switch.

Search paths for config/script files can be added to OpenOCD by using the -s <search> switch. The current directory and the OpenOCD target library is in the search path by default.

Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection with the target. In general, it is possible for the JTAG controller to be unresponsive until the target is set up correctly via e.g. GDB monitor commands in a GDB init script.

Configuration
*************

OpenOCD runs as a daemon, and reads it current configuration by default from the file openocd.cfg in the current directory. A different configuration file can be specified with the  -f <conf.file> command line switch specified when starting OpenOCD.

The configuration file is used to specify on which ports the daemon listens for new connections, the JTAG interface used to connect to the target, the layout of the JTAG chain, the targets that should be debugged, and connected flashes.

Daemon configuration
====================

  * init

     This command terminates the configuration stage and enters the normal command mode. This can be useful to add commands to the startup scripts and commands such as resetting the target, programming flash, etc. To reset the CPU upon startup, add "init" and "reset" at the end of the config script or at the end of the OpenOCD command line using the -c command line switch.

  * telnet_port <NUMBER>

     Port on which to listen for incoming telnet connections

  * tcl_port <NUMBER>

     Port on which to listen for incoming TCL syntax. This port is intended as a simplified RPC connection that can be used by clients to issue commands and get the output from the TCL engine.

  * gdb_port <NUMBER>

     First port on which to listen for incoming GDB connections. The GDB port for the first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.

  * gdb_breakpoint_override <HARD|SOFT|DISABLED>

     Force breakpoint type for gdb 'break' commands. The raison d'etre for this option is to support GDB GUI's without a hard/soft breakpoint concept where the default OpenOCD and GDB behaviour is not sufficient. Note that GDB will use hardware breakpoints if the memory map has been set up for flash regions.

     This option replaces older arm7_9 target commands that addressed the same issue.

  * gdb_detach <RESUME|RESET|HALT|NOTHING>

     Configures what OpenOCD will do when gdb detaches from the daeman. Default behaviour is <RESUME>

  * gdb_memory_map <ENABLE|DISABLE>

     Set to <ENABLE> to cause OpenOCD to send the memory configuration to gdb when requested. gdb will then know when to set hardware breakpoints, and program flash using the gdb load command. gdb_flash_program enable will also need enabling for flash programming to work. Default behaviour is <ENABLE> See gdb_flash_program.

  * gdb_flash_program <ENABLE|DISABLE>

     Set to <ENABLE> to cause OpenOCD to program the flash memory when a vFlash packet is received. Default behaviour is <ENABLE>

JTAG interface configuration
============================

  * interface <NAME>

     Use the interface driver <NAME> to connect to the target. Currently supported interfaces are

       - parport PC parallel port bit-banging (Wigglers, PLD download cable, ...)

       - amt_jtagaccel Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP mode parallel port

       - ft2232 FTDI FT2232 based devices using either the open-source libftdi or the binary only FTD2XX driver. The FTD2XX is superior in performance, but not available on every platform. The libftdi uses libusb, and should be portable to all systems that provide libusb.

       - ep93xx Cirrus Logic EP93xx based single-board computer bit-banging (in development)

       - presto ASIX PRESTO USB JTAG programmer.

       - usbprog usbprog is a freely programmable USB adapter.

       - gw16012 Gateworks GW16012 JTAG programmer.

       - jlink Segger jlink usb adapter

  * jtag_speed <RESET SPEED>

     Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum speed. The actual effect of this option depends on the JTAG interface used.

     The speed used during reset can be adjusted using setting jtag_speed during pre_reset and post_reset events.

       - wiggler: maximum speed / NUMBER

       - ft2232: 6MHz / (NUMBER+1)

       - amt jtagaccel: 8 / 2**NUMBER

       - jlink: maximum speed in kHz (0-12000), 0 will use RTCK

     Note: Make sure the jtag clock is no more than 1/6th × CPU-Clock. This is especially true for synthesized cores (-S).

  * jtag_khz <RESET SPEED KHZ>

     Same as jtag_speed, except that the speed is specified in maximum kHz. If the device can not support the rate asked for, or can not translate from kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK is not supported, then an error is reported.

  * reset_config <SIGNALS> [COMBINATION] [TRST_TYPE] [SRST_TYPE]

     The configuration of the reset signals available on the JTAG interface AND the target. If the JTAG interface provides SRST, but the target doesn't connect that signal properly, then OpenOCD can't use it. <SIGNALS> can be none, trst_only, srst_only or trst_and_srst.

     [COMBINATION] is an optional value specifying broken reset signal implementations. srst_pulls_trst states that the testlogic is reset together with the reset of the system (e.g. Philips LPC2000, "broken" board layout), trst_pulls_srst says that the system is reset together with the test logic (only hypothetical, I haven't seen hardware with such a bug, and can be worked around). combined imples both srst_pulls_trst and trst_pulls_srst. The default behaviour if no option given is separate.

     The [TRST_TYPE] and [SRST_TYPE] parameters allow the driver type of the reset lines to be specified. Possible values are trst_push_pull (default) and trst_open_drain for the test reset signal, and srst_open_drain (default) and srst_push_pull for the system reset. These values only affect JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.

  * jtag_device <IR LENGTH> <IR CAPTURE> <IR MASK> <IDCODE INSTRUCTION>

     Describes the devices that form the JTAG daisy chain, with the first device being the one closest to TDO. The parameters are the length of the instruction register (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9). The IDCODE instruction will in future be used to query devices for their JTAG identification code. This line is the same for all ARM7 and ARM9 devices. Other devices, like CPLDs, require different parameters. An example configuration line for a Xilinx XC9500 CPLD would look like this:

          jtag_device 8 0x01 0x0e3 0xfe

     The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary. The IDCODE instruction is 0xfe.

  * jtag_nsrst_delay <MS>

     How long (in milliseconds) OpenOCD should wait after deasserting nSRST before starting new JTAG operations.

  * jtag_ntrst_delay <MS>

     Same jtag_nsrst_delay, but for nTRST

     The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor, or on-chip features) keep a reset line asserted for some time after the external reset got deasserted.

parport options
===============

  * parport_port <NUMBER>

     Either the address of the I/O port (default: 0x378 for LPT1) or the number of the /dev/parport device

     When using PPDEV to access the parallel port, use the number of the parallel port: parport_port 0 (the default). If parport_port 0x378 is specified you may encounter a problem.

  * parport_cable <NAME>

     The layout of the parallel port cable used to connect to the target. Currently supported cables are

       - wiggler The original Wiggler layout, also supported by several clones, such as the Olimex ARM-JTAG

       - wiggler2 Same as original wiggler except an led is fitted on D5.

       - wiggler_ntrst_inverted Same as original wiggler except TRST is inverted.

       - old_amt_wiggler The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new version available from the website uses the original Wiggler layout ('WIGGLER')

       - chameleon The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to program the Chameleon itself, not a connected target.

       - dlc5 The Xilinx Parallel cable III.

       - triton The parallel port adapter found on the 'Karo Triton 1 Development Board'. This is also the layout used by the HollyGates design (see http://www.lartmaker.nl/projects/jtag/).

       - flashlink The ST Parallel cable.

       - arm-jtag Same as original wiggler except SRST and TRST connections reversed and TRST is also inverted.

       - altium Altium Universal JTAG cable.

  * parport_write_on_exit <ON|OFF>

     This will configure the parallel driver to write a known value to the parallel interface on exiting OpenOCD

amt_jtagaccel options
=====================

  * parport_port <NUMBER>

     Either the address of the I/O port (default: 0x378 for LPT1) or the number of the /dev/parport device

ft2232 options
==============

  * ft2232_device_desc <DESCRIPTION>

     The USB device description of the FTDI FT2232 device. If not specified, the FTDI default value is used. This setting is only valid if compiled with FTD2XX support.

  * ft2232_serial <SERIAL-NUMBER>

     The serial number of the FTDI FT2232 device. If not specified, the FTDI default values are used.

  * ft2232_layout <NAME>

     The layout of the FT2232 GPIO signals used to control output-enables and reset signals. Valid layouts are

       - usbjtag "USBJTAG-1" layout described in the original OpenOCD diploma thesis

       - jtagkey Amontec JTAGkey and JTAGkey-tiny

       - signalyzer Signalyzer

       - olimex-jtag Olimex ARM-USB-OCD

       - m5960 American Microsystems M5960

       - evb_lm3s811 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or SRST signals on external connector

       - comstick Hitex STR9 comstick

       - stm32stick Hitex STM32 Performance Stick

       - flyswatter Tin Can Tools Flyswatter

       - turtelizer2 egnite Software turtelizer2

       - oocdlink OOCDLink

  * ft2232_vid_pid <VID> <PID>

     The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI default values are used. Multiple <VID>, <PID> pairs may be given, eg.

          ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003

  * ft2232_latency <MS>

     On some systems using ft2232 based JTAG interfaces the FT_Read function call in ft2232_read() fails to return the expected number of bytes. This can be caused by USB communication delays and has proved hard to reproduce and debug. Setting the FT2232 latency timer to a larger value increases delays for short USB packages but it also reduces the risk of timeouts before receiving the expected number of bytes. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.

ep93xx options
==============

Currently, there are no options available for the ep93xx interface.

Target configuration
====================

  * target <TYPE> <ENDIANESS> <JTAG POS> <VARIANT>

     Defines a target that should be debugged. Currently supported types are:

       - arm7tdmi

       - arm720t

       - arm9tdmi

       - arm920t

       - arm922t

       - arm926ejs

       - arm966e

       - cortex_m3

       - feroceon

       - xscale

       - arm11

       - mips_m4k

     If you want to use a target board that is not on this list, see Adding a new target board. The target types command can be used to get the list of targets supported from within openocd.

     Endianess may be little or big.

  * target_script <TARGET#> <EVENT> <SCRIPT_FILE>

     Event is one of the following: pre_reset, reset, post_reset, post_halt, pre_resume or gdb_program_config. post_reset and reset will produce the same results.

  * working_area <TARGET#> <ADDRESS> <SIZE> <BACKUP|NOBACKUP> [virtual address]

     Specifies a working area for the debugger to use. This may be used to speed-up downloads to target memory and flash operations, or to perform otherwise unavailable operations (some coprocessor operations on ARM7/9 systems, for example). The last parameter decides whether the memory should be preserved (<BACKUP>) or can simply be overwritten (<NOBACKUP>). If possible, use a working_area that doesn't need to be backed up, as performing a backup slows down operation.

arm7tdmi options
----------------

target arm7tdmi <ENDIANESS> <JTAG#>

The arm7tdmi target definition requires at least one additional argument, specifying the position of the target in the JTAG daisy-chain. The first JTAG device is number 0. The optional [VARIANT] parameter has been removed in recent versions. The correct feature set is determined at runtime.

arm720t options
---------------

ARM720t options are similar to ARM7TDMI options.

arm9tdmi options
----------------

ARM9TDMI options are similar to ARM7TDMI options. Supported variants are arm920t, arm922t and arm940t. This enables the hardware single-stepping support found on these cores.

arm920t options
---------------

ARM920t options are similar to ARM9TDMI options.

arm966e options
---------------

ARM966e options are similar to ARM9TDMI options.

cortex_m3 options
-----------------

use variant <VARIANT> lm3s when debugging luminary lm3s targets. This will cause openocd to use a software reset rather than asserting SRST to avoid a issue with clearing the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will be detected and the normal reset behaviour used.

xscale options
--------------

Supported variants are ixp42x, ixp45x, ixp46x, pxa250, pxa255, pxa26x.

arm11 options
-------------

mips_m4k options
----------------

Use variant ejtag_srst when debugging targets that do not provide a functional SRST line on the EJTAG connector. This causes openocd to instead use an EJTAG software reset command to reset the processor. You still need to enable srst on the reset configuration command to enable openocd hardware reset functionality.

Flash configuration
===================

  * flash bank <DRIVER> <BASE> <SIZE> <CHIP_WIDTH> <BUS_WIDTH> <TARGET#> [DRIVER_OPTIONS ...]

     Configures a flash bank at <BASE> of <SIZE> bytes and <CHIP_WIDTH> and <BUS_WIDTH> bytes using the selected flash <driver>.

lpc2000 options
---------------

flash bank lpc2000 <BASE> <SIZE> 0 0 <TARGET#> <VARIANT> <CLOCK> [CALC_CHECKSUM]

LPC flashes don't require the chip and bus width to be specified. Additional parameters are the <VARIANT>, which may be LPC2000_V1 (older LPC21xx and LPC22xx) or LPC2000_V2 (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number of the target this flash belongs to (first is 0), the frequency at which the core is currently running (in kHz - must be an integral number), and the optional keyword CALC_CHECKSUM, telling the driver to calculate a valid checksum for the exception vector table.

cfi options
-----------

flash bank cfi <BASE> <SIZE> <CHIP_WIDTH> <BUS_WIDTH> <TARGET#> [JEDEC_PROBE|X16_AS_X8]

CFI flashes require the number of the target they're connected to as an additional argument. The CFI driver makes use of a working area (specified for the target) to significantly speed up operation.

CHIP_WIDTH and BUS_WIDTH are specified in bytes.

The JEDEC_PROBE option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.

X16_AS_X8 ???

at91sam7 options
----------------

flash bank at91sam7 0 0 0 0 <TARGET#>

AT91SAM7 flashes only require the TARGET#, all other values are looked up after reading the chip-id and type.

str7 options
------------

flash bank str7x <BASE> <SIZE> 0 0 <TARGET#> <VARIANT>

variant can be either STR71x, STR73x or STR75x.

str9 options
------------

flash bank str9x <BASE> <SIZE> 0 0 <TARGET#>

The str9 needs the flash controller to be configured prior to Flash programming, eg.

     str9x flash_config 0 4 2 0 0x80000

This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.

str9 options (str9xpec driver)
------------------------------

flash bank str9xpec <BASE> <SIZE> 0 0 <TARGET#>

Before using the flash commands the turbo mode will need enabling using str9xpec enable_turbo <NUM>.

Only use this driver for locking/unlocking the device or configuring the option bytes. Use the standard str9 driver for programming.

stellaris (LM3Sxxx) options
---------------------------

flash bank stellaris <BASE> <SIZE> 0 0 <TARGET#>

stellaris flash plugin only require the TARGET#.

stm32x options
--------------

flash bank stm32x <BASE> <SIZE> 0 0 <TARGET#>

stm32x flash plugin only require the TARGET#.

aduc702x options
----------------

flash bank aduc702x <BASE> <SIZE> 0 0 <TARGET#>

aduc702x flash plugin require the flash BASE, SIZE and TARGET#.

mFlash configuration
====================

  * mflash bank <SOC> <BASE> <CHIP_WIDTH> <BUS_WIDTH> <RST PIN> <WP PIN> <DPD PIN> <TARGET #>

     Configures a mflash for <SOC> host bank at <BASE>. <CHIP_WIDTH> and <BUS_WIDTH> are bytes order. Pin number format is dependent on host GPIO calling convention. If WP or DPD pin was not used, write -1. Currently, mflash bank support s3c2440 and pxa270.

(ex. of s3c2440) mflash <RST PIN> is GPIO B1, <WP PIN> and <DPD PIN> are not used.

     mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0

(ex. of pxa270) mflash <RST PIN> is GPIO 43, <DPD PIN> is not used and <DPD PIN> is GPIO 51.

     mflash bank pxa270 0x08000000 2 2 43 -1 51 0

Target library
**************

OpenOCD comes with a target configuration script library. These scripts can be used as-is or serve as a starting point.

The target library is published together with the openocd executable and the path to the target library is in the OpenOCD script search path. Similarly there are example scripts for configuring the JTAG interface.

The command line below uses the example parport configuration scripts that ship with OpenOCD, then configures the str710.cfg target and finally issues the init and reset command. The communication speed is set to 10kHz for reset and 8MHz for post reset.

     openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"

To list the target scripts available:

     $ ls  /usr/local/lib/openocd/target

     arm7_fast.cfg    lm3s6965.cfg  pxa255.cfg      stm32.cfg   xba_revA3.cfg
     at91eb40a.cfg    lpc2148.cfg   pxa255_sst.cfg  str710.cfg  zy1000.cfg
     at91r40008.cfg   lpc2294.cfg   sam7s256.cfg    str912.cfg
     at91sam9260.cfg  nslu2.cfg     sam7x256.cfg    wi-9c.cfg

Commands
********

OpenOCD allows user interaction through a GDB server (default: port 3333), a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter is available from both the telnet interface and a GDB session. To issue commands to the interpreter from within a GDB session, use the monitor command, e.g. use monitor poll to issue the poll command. All output is relayed through the GDB session.

The TCL interface is used as a simplified RPC mechanism that feeds all the input into the TCL interpreter and returns the output from the evaluation of the commands.

Daemon
======

  * sleep <MSEC>

     Wait for n milliseconds before resuming. Useful in connection with script files (SCRIPT command and TARGET_SCRIPT configuration).

  * shutdown

     Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).

  * debug_level [N]

     Display or adjust debug level to n<0-3>

  * fast [ENABLE|DISABLE]

     Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory downloads and fast memory access will work if the JTAG interface isn't too fast and the core doesn't run at a too low frequency. Note that this option only changes the default and that the indvidual options, like DCC memory downloads, can be enabled and disabled individually.

     The target specific "dangerous" optimisation tweaking options may come and go as more robust and user friendly ways are found to ensure maximum throughput and robustness with a minimum of configuration.

     Typically the "fast enable" is specified first on the command line:

          openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg

  * log_output <FILE>

     Redirect logging to <file> (default: stderr)

  * script <FILE>

     Execute commands from <file>

Target state handling
---------------------

  * power <ON|OFF>

     Turn power switch to target on/off. No arguments: print status.

  * reg [#|name] [value]

     Access a single register by its number[#] or by its [name]. No arguments: list all available registers for the current target. Number or name argument: display a register Number or name and value arguments: set register value

  * poll [on|off]

     Poll the target for its current state. If the target is in debug mode, architecture specific information about the current state is printed. An optional parameter allows continuous polling to be enabled and disabled.

  * halt [ms]

     Send a halt request to the target and wait for it to halt for up to [ms] milliseconds. Default [ms] is 5 seconds if no arg given. Optional arg ms is a timeout in milliseconds. Using 0 as the [ms] will stop OpenOCD from waiting.

  * wait_halt [ms]

     Wait for the target to enter debug mode. Optional [ms] is a timeout in milliseconds. Default [ms] is 5 seconds if no arg given.

  * resume [ADDRESS]

     Resume the target at its current code position, or at an optional address. OpenOCD will wait 5 seconds for the target to resume.

  * step [ADDRESS]

     Single-step the target at its current code position, or at an optional address.

  * reset [run|halt|init]

     Perform a hard-reset. The optional parameter specifies what should happen after the reset.

     With no arguments a "reset run" is executed

       - run

          Let the target run.

       - halt

          Immediately halt the target (works only with certain configurations).

       - init

          Immediately halt the target, and execute the reset script (works only with certain configurations)

  * soft_reset_halt

     Requesting target halt and executing a soft reset.

Memory access commands
----------------------

  * meminfo

     display available ram memory.

These commands allow accesses of a specific size to the memory system:

  * mdw <ADDR> [COUNT]

     display memory words

  * mdh <ADDR> [COUNT]

     display memory half-words

  * mdb <ADDR> [COUNT]

     display memory bytes

  * mww <ADDR> <VALUE>

     write memory word

  * mwh <ADDR> <VALUE>

     write memory half-word

  * mwb <ADDR> <VALUE>

     write memory byte

  * load_image <FILE> <ADDRESS> [bin|ihex|elf]

     Load image <FILE> to target memory at <ADDRESS>

  * fast_load_image <FILE> <ADDRESS> [bin|ihex|elf]

     Normally you should be using load_image or GDB load. However, for testing purposes or when IO overhead is significant(OpenOCD running on embedded host), then storing the image in memory and uploading the image to the target can be a way to upload e.g. multiple debug sessions when the binary does not change. Arguments as load_image, but image is stored in OpenOCD host memory, i.e. does not affect target.  This approach is also useful when profiling target programming performance as IO and target programming can easily be profiled seperately.

  * fast_load

     Loads image stored in memory by fast_load_image to current target. Must be preceeded by fast_load_image.

  * dump_image <FILE> <ADDRESS> <SIZE>

     Dump <SIZE> bytes of target memory starting at <ADDRESS> to a (binary) <FILE>.

  * verify_image <FILE> <ADDRESS> [bin|ihex|elf]

     Verify <FILE> against target memory starting at <ADDRESS>. This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.

Breakpoint commands
-------------------

  * bp <ADDR> <LEN> [HW]

     set breakpoint <address> <length> [hw]

  * rbp <ADDR>

     remove breakpoint <adress>

  * wp <ADDR> <LEN> <R|W|A> [VALUE] [MASK]

     set watchpoint <address> <length> <r/w/a> [value] [mask]

  * rwp <ADDR>

     remove watchpoint <adress>

Flash commands
--------------

  * flash banks

     List configured flash banks

  * flash info <NUM>

     Print info about flash bank <num>

  * flash probe <NUM>

     Identify the flash, or validate the parameters of the configured flash. Operation depends on the flash type.

  * flash erase_check <NUM>

     Check erase state of sectors in flash bank <NUM>. This is the only operation that updates the erase state information displayed by flash info. That means you have to issue an erase_check command after erasing or programming the device to get updated information.

  * flash protect_check <NUM>

     Check protection state of sectors in flash bank <num>. flash erase_sector using the same syntax.

  * flash erase_sector <NUM> <FIRST> <LAST>

     Erase sectors at bank <NUM>, starting at sector <FIRST> up to and including <LAST>. Sector numbering starts at 0. Depending on the flash type, erasing may require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using the CFI driver).

  * flash erase_address <ADDRESS> <LENGTH>

     Erase sectors starting at <ADDRESS> for <LENGTH> bytes

  * flash write_bank <NUM> <FILE> <OFFSET>

     Write the binary <FILE> to flash bank <NUM>, starting at <offset> bytes from the beginning of the bank.

  * flash write_image [ERASE] <FILE> [OFFSET] [TYPE]

     Write the image <FILE> to the current target's flash bank(s). A relocation [OFFSET] can be specified and the file [TYPE] can be specified explicitly as bin (binary), ihex (Intel hex), elf (ELF file) or s19 (Motorola s19). Flash memory will be erased prior to programming if the erase parameter is given.

  * flash protect <NUM> <FIRST> <LAST> <on|off>

     Enable (ON) or disable (OFF) protection of flash sectors <FIRST> to <LAST> of flash bank <NUM>.

mFlash commands
---------------

  * mflash probe Probe mflash.

  * mflash write <NUM> <FILE> <OFFSET> Write the binary <FILE> to mflash bank <NUM>, starting at <OFFSET> bytes from the beginning of the bank.

  * mflash dump <NUM> <FILE> <OFFSET> <SIZE> Dump <size> bytes, starting at <OFFSET> bytes from the beginning of the <NUM> bank to a <FILE>.

Target Commands
===============

Overview
--------

Pre "TCL" - many commands in OpenOCD where implemented as C functions. Post "TCL" (Jim-Tcl to be more exact, June 2008) TCL became a bigger part of OpenOCD.

One of the biggest changes is the introduction of 'target specific' commands. When every time you create a target, a special command name is created specifically for that target. For example - in TCL/TK - if you create a button (or any other screen object) you can specify various "button configuration parameters". One of those parameters is the "object cmd/name" [ In TK - this is referred to as the object path ]. Later you	can use that 'path' as a command to modify the button, for example to make it "grey", or change the color. In effect, the "path" function is an 'object oriented command'. The TCL change in OpenOCD follows the same principle, you create a target, and a specific "targetname" command is created.

There are two methods of creating a target:

 1. Using the old syntax (deprecated). Target names are autogenerated as: "target0", "target1", etc.;

 2. Using the new syntax, you can specify the name of the target.

As most users will have a single JTAG target, and by default the command name will probably default to "target0", thus for reasons of simplicity the instructions below use the name "target0".

Commands
--------

OpenOCD has the following 'target' or 'target-like' commands:

 1. targets (plural) - lists all known targets and a little bit of information about each target, most importantly the target *COMMAND*NAME* (it also lists the target number);

 2. target (singular) - used to create, configure list, etc the targets;

 3. target0 - the command object for the first target. Unless you specified another name.

Targets Command
...............

The "targets" command has 2 functions:

  * With a parameter, you can change the current command line target.

     NOTE: "with a parameter" is really only useful with 'multiple JTAG targets' not something you normally encounter (ie: If you had 2 arm chips - sharing the same JTAG chain).
     # using a target name.
     (gdb) mon targets target0
     # or a target by number.
     (gdb) mon targets 3

  * Plain, without any parameter lists targets, for example:

     (gdb) mon targets
           CmdName     Type     Endian    ChainPos   State
     --  ---------- ---------- ---------- -------- ----------
         0: target0  arm7tdmi   little        0      halted

     This shows:

      a. in this example, a single target;

      b. target number 0 (1st column);

      c. the 'object name' is target0 (the default name);

      d. it is an arm7tdmi;

      e. little endian;

      f. the position in the JTAG chain;

      g. and is currently halted.

Target Command
..............

The "target" command has the following options:

  * target create

     	target create CMDNAME TYPE  ... config options ...
     		argv[0] = 'target'
     		argv[1] = 'create'
     		argv[2] = the 'object command'
     	               (normally, target0, see (3) above)
     		argv[3] = the target type, ie: arm7tdmi
     		argv[4..N] = configuration parameters

  * target types

     Lists all supported target types; ie: arm7tdmi, xscale, fericon, cortex-m3. The result TCL list of all known target types (and is human readable).

  * target names

     Returns a TCL list of all known target commands (and is human readable).

     Example:
     	foreach t [target names] {
     	    puts [format "Target: %s\n" $t]
     	}

  * target current

     Returns the TCL command name of the current target.

     Example:
     	set ct [target current]
     	set t  [$ct cget -type]

     	puts "Current target name is: $ct, and is a: $t"

  * target number <VALUE>

     Returns the TCL command name of the specified target.

     Example
         set thename [target number $x]
         puts [format "Target %d is: %s\n" $x $thename]
     For instance, assuming the defaults
         target number 0
     Would return 'target0' (or whatever you called it)

  * target count

     Returns the larget+1 target number.

     Example:
         set c [target count]
         for { set x 0 } { $x < $c } { incr x } {
            	# Assuming you have this function..
            	print_target_details $x
         }

Target0 Command
...............

The "target0" command (the "Target Object" command):

Once a target is 'created' a command object by that targets name is created, for example
	target create BiGRed arm7tdmi -endian little -chain-position 3

Would create a [case sensitive] "command" BiGRed

If you use the old [deprecated] syntax, the name is automatically generated and is in the form:
	target0, target1, target2, target3, ... etc.

Target CREATE, CONFIGURE and CGET Options Command
.................................................

The commands:
    target create CMDNAME TYPE  [configure-options]
    CMDNAME configure [configure-options]
    CMDNAME cget      [configure-options]

  * In the 'create' case, one is creating the target and can specify any number of configuration parameters.

  * In the 'CMDNAME configure' case, one can change the setting [Not all things can, or should be changed].

  * In the 'CMDNAME cget' case, the goal is to query the target for a specific configuration option.

In the above, the "default" name target0 is 'target0'.

Example:

From the (gdb) prompt, one can type this:

	(gdb) mon target0 configure -endian big

And change target0 to 'big-endian'.  This is a contrived example, specifically for this document - don't expect changing endian 'mid-operation' to work you should set the endian at creation.

Known options [30/august/2008] are:

  * [Mandatory 'create' Options]

       * type arm7tdmi|arm720|etc ...

       * chain-position NUMBER

       * endian ENDIAN

  * Optional

       * event EVENTNAME  "tcl-action"

       * reset RESETACTION

       * work-area-virt ADDR

       * work-area-phys ADDR

       * work-area-size ADDR

       * work-area-backup BOOLEAN

Hint: To get a list of available options, try this:
	(gdb) mon target0 cget -BLAHBLAHBLAH

the above causes an error - and a helpful list of valid options.

One can query any of the above options at run time, for example:
 (gdb) mon target0 cget -OPTION [param]

Example TCL script

    # For all targets...
    set c [target count]
    for { set x 0 } { $x < $c } { incr x ] {
      set n [target number $x]
      set t [$n cget -type]
      set e [$n cget -endian]
      puts [format "%d: %s, %s, endian: %s\n" $x $n $t $n]
   }

Might produce:

    0: pic32chip, mips_m4k, endain: little
    1: arm7, arm7tdmi, endian: big
    2: blackfin, bf534, endian: little

Notice the above example is not target0, target1, target2 Why? Because in this contrived multi-target example - more human understandable target names might be helpful.

For example these two are the same:

   (gdb) mon blackfin configure -event FOO {puts "Hi mom"}

or:

   (gdb) mon [target number 2] configure -event FOO {puts "Hi mom"}

In the second case, we use [] to get the command name of target #2, in this contrived example - it is "blackfin".

Two important configuration options are:

"-event" and "-reset"

The "-reset" option specifies what should happen when the chip is reset, for example should it 'halt', 're-init', or what.

The "-event" option less you specify a TCL command to occur when a specific event occurs.

Other Target Commands
.....................

  * profile <SECONDS> <GMON.OUT>

     Profiling samples the CPU PC as quickly as OpenOCD is able, which will be used as a random sampling of PC.

Target Events
-------------

Overview
........

At various points in time - certain 'target' events happen.  You can create a custom event action to occur at that time. For example - after reset, the PLLs and CLOCKs may need to be reconfigured, or perhaps the SDRAM needs to be re-initialized. Often the easiest way to do that is to create a simple script file containing the series of (mww [poke memory]) commands you would type by hand, to reconfigure the target clocks. You could specify the "event action" like this:

   (gdb) mon target0 configure -event reset-init "script cfg.clocks"

In the above example, when the event "reset-init" occurs, the "action-string" will be evaluated as if you typed it at the console:

  * Option1 - The simple approach (above) is to create a script file with lots of "mww" (memory write word) commands to configure your targets clocks and/or external memory;

  * Option2 -	You can instead create a fancy TCL procedure and invoke that procedure instead of sourcing a file [In fact, "script" is a TCL procedure that loads a file].

Details
.......

There are many events one could use, to get a current list of events type the following invalid command, you'll get a helpful "runtime error" message, see below [list valid as of 30/august/2008]:

(gdb) mon target0 cget -event FAFA
Runtime error, file "../../../openocd23/src/helper/command.c", line 433:
	-event: Unknown: FAFA, try one of: old-pre_reset,
	old-gdb_program_config, old-post_reset, halted,
	resumed, resume-start, resume-end, reset-start,
	reset-assert-pre, reset-assert-post,
	reset-deassert-pre, reset-deassert-post,
	reset-halt-pre, reset-halt-post, reset-wait-pre,
	reset-wait-post, reset-init, reset-end,
	examine-start, examine-end, debug-halted,
	debug-resumed, gdb-attach, gdb-detach,
	gdb-flash-write-start, gdb-flash-write-end,
	gdb-flash-erase-start, gdb-flash-erase-end,
	resume-start, resume-ok, or resume-end

NOTE: The event-names "old-*" are deprecated and exist only to help old scripts continue to function, and the old "target_script" command to work. Please do not rely on them.

These are some other important names:

  * gdb-flash-erase-start

  * gdb-flash-erase-end

  * gdb-flash-write-start

  * gdb-flash-write-end

These occur when GDB/OpenOCD attempts to erase & program the FLASH chip via GDB. For example - some PCBs may have a simple GPIO pin that acts like a "flash write protect" you might need to write a script that disables "write protect".

To get a list of current 'event actions', type the following command:

   (gdb) mon target0 eventlist

    Event actions for target (0) target0

    Event                     | Body
    ------------------------- | ----------------------------------------
    old-post_reset            | script event/sam7x256_reset.script

Here is a simple example for all targets:

   (gdb)  mon foreach x [target names] { $x eventlist }

The above uses some TCL tricks:

 a. foreach VARIABLE  LIST  BODY

 b. to generate the list, we use [target names]

 c. the BODY, contains $x - the loop variable and expands to the target specific name

Recalling the earlier discussion - the "object command" there are other things you can do besides "configure" the target.

Note: Many of these commands exist as "global" commands, and they also exist as target specific commands. For example, the "mww" (memory write word) operates on the current target if you have more then 1 target, you must switch. In contrast to the normal commands, these commands operate on the specific target. For example, the command "mww" writes data to the *current* command line target.

Often, you have only a single target - but if you have multiple targets (ie: a PIC32 and an at91sam7 - your reset-init scripts might get a bit more complicated, ie: you must specify which of the two chips you want to write to. Writing 'pic32' clock configuration to an at91sam7 does not work).

The commands are [as of 30/august/2008]:
    TNAME  mww ADDRESS VALUE
    TNAME  mwh ADDRESS VALUE
    TNAME  mwb ADDRESS VALUE
    	   Write(poke): 32, 16, 8bit values to memory.

    TNAME  mdw ADDRESS VALUE
    TNAME  mdh ADDRESS VALUE
    TNAME  mdb ADDRESS VALUE
    	   Human 'hexdump' with ascii 32, 16, 8bit values

    TNAME  mem2array  [see mem2array command]
    TNAME  array2mem  [see array2mem command]

    TNAME  curstate
    	   Returns the current state of the target.

    TNAME  examine
    	   See 'advanced target reset'
    TNAME  poll
    	   See 'advanced target reset'
    TNAME  reset assert
    	   See 'advanced target reset'
    TNAME  reset deassert
    	   See 'advanced target reset'
    TNAME  halt
    	   See 'advanced target reset'
    TNAME  waitstate STATENAME
    	   See 'advanced target reset'

Target Specific Commands
========================

AT91SAM7 specific commands
--------------------------

The flash configuration is deduced from the chip identification register. The flash controller handles erases automatically on a page (128/265 byte) basis so erase is not necessary for flash programming. AT91SAM7 processors with less than 512K flash only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes that can be erased separatly. Only an EraseAll command is supported by the controller for each flash plane and this is called with

  * flash erase <NUM> FIRST_PLANE LAST_PLANE

     bulk erase flash planes first_plane to last_plane.

  * at91sam7 gpnvm <NUM> <BIT> <set|clear>

     set or clear a gpnvm bit for the processor

STR9 specific commands
----------------------

These are flash specific commands when using the str9xpec driver.

  * str9xpec enable_turbo <NUM>

     enable turbo mode, simply this will remove the str9 from the chain and talk directly to the embedded flash controller.

  * str9xpec disable_turbo <NUM>

     restore the str9 into jtag chain.

  * str9xpec lock <NUM>

     lock str9 device. The str9 will only respond to an unlock command that will erase the device.

  * str9xpec unlock <NUM>

     unlock str9 device.

  * str9xpec options_read <NUM>

     read str9 option bytes.

  * str9xpec options_write <NUM>

     write str9 option bytes.

STR9 configuration
------------------

  * str9x flash_config <BANK> <BBSR> <NBBSR> <BBADR> <NBBADR>

     Configure str9 flash controller.

          eg. str9x flash_config 0 4 2 0 0x80000
          This will setup
          BBSR - Boot Bank Size register
          NBBSR - Non Boot Bank Size register
          BBADR - Boot Bank Start Address register
          NBBADR - Boot Bank Start Address register

STR9 option byte configuration
------------------------------

  * str9xpec options_cmap <NUM> <bank0|bank1>

     configure str9 boot bank.

  * str9xpec options_lvdthd <NUM> <2.4v|2.7v>

     configure str9 lvd threshold.

  * str9xpec options_lvdsel <NUM> <vdd|vdd_vddq>

     configure str9 lvd source.

  * str9xpec options_lvdwarn <BANK> <vdd|vdd_vddq>

     configure str9 lvd reset warning source.

STM32x specific commands
------------------------

These are flash specific commands when using the stm32x driver.

  * stm32x lock <NUM>

     lock stm32 device.

  * stm32x unlock <NUM>

     unlock stm32 device.

  * stm32x options_read <NUM>

     read stm32 option bytes.

  * stm32x options_write <NUM> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>

     write stm32 option bytes.

  * stm32x mass_erase <NUM>

     mass erase flash memory.

Stellaris specific commands
---------------------------

These are flash specific commands when using the Stellaris driver.

  * stellaris mass_erase <NUM>

     mass erase flash memory.

Architecture Specific Commands
==============================

ARMV4/5 specific commands
-------------------------

These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems or Intel XScale (XScale isn't supported yet).

  * armv4_5 reg

     Display a list of all banked core registers, fetching the current value from every core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current register value.

  * armv4_5 core_mode [ARM|THUMB]

     Displays the core_mode, optionally changing it to either ARM or Thumb mode. The target is resumed in the currently set core_mode.

ARM7/9 specific commands
------------------------

These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t, ARM920t or ARM926EJ-S.

  * arm7_9 dbgrq <ENABLE|DISABLE>

     Enable use of the DBGRQ bit to force entry into debug mode. This should be safe for all but ARM7TDMI--S cores (like Philips LPC).

  * arm7_9 fast_memory_access <ENABLE|DISABLE>

     Allow OpenOCD to read and write memory without checking completion of the operation. This provides a huge speed increase, especially with USB JTAG cables (FT2232), but might be unsafe if used with targets running at a very low speed, like the 32kHz startup clock of an AT91RM9200.

  * arm7_9 dcc_downloads <ENABLE|DISABLE>

     Enable the use of the debug communications channel (DCC) to write larger (>128 byte) amounts of memory. DCC downloads offer a huge speed increase, but might be potentially unsafe, especially with targets running at a very low speed. This command was introduced with OpenOCD rev. 60.

ARM720T specific commands
-------------------------

  * arm720t cp15 <NUM> [VALUE]

     display/modify cp15 register <num> [value].

  * arm720t md<bhw>_phys <ADDR> [COUNT]

     Display memory at physical address addr.

  * arm720t mw<bhw>_phys <ADDR> <VALUE>

     Write memory at physical address addr.

  * arm720t virt2phys <VA>

     Translate a virtual address to a physical address.

ARM9TDMI specific commands
--------------------------

  * arm9tdmi vector_catch <ALL|NONE>

     Catch arm9 interrupt vectors, can be all none or any of the following: reset undef swi pabt dabt reserved irq fiq.

     Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.

ARM966E specific commands
-------------------------

  * arm966e cp15 <NUM> [VALUE]

     display/modify cp15 register <num> [value].

ARM920T specific commands
-------------------------

  * arm920t cp15 <NUM> [VALUE]

     display/modify cp15 register <num> [value].

  * arm920t cp15i <NUM> [VALUE] [ADDRESS]

     display/modify cp15 (interpreted access) <opcode> [value] [address]

  * arm920t cache_info

     Print information about the caches found. This allows you to see if your target is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).

  * arm920t md<bhw>_phys <ADDR> [COUNT]

     Display memory at physical address addr.

  * arm920t mw<bhw>_phys <ADDR> <VALUE>

     Write memory at physical address addr.

  * arm920t read_cache <FILENAME>

     Dump the content of ICache and DCache to a file.

  * arm920t read_mmu <FILENAME>

     Dump the content of the ITLB and DTLB to a file.

  * arm920t virt2phys <VA>

     Translate a virtual address to a physical address.

ARM926EJS specific commands
---------------------------

  * arm926ejs cp15 <NUM> [VALUE]

     display/modify cp15 register <num> [value].

  * arm926ejs cache_info

     Print information about the caches found.

  * arm926ejs md<bhw>_phys <ADDR> [COUNT]

     Display memory at physical address addr.

  * arm926ejs mw<bhw>_phys <ADDR> <VALUE>

     Write memory at physical address addr.

  * arm926ejs virt2phys <VA>

     Translate a virtual address to a physical address.

CORTEX_M3 specific commands
---------------------------

  * cortex_m3 maskisr <ON|OFF>

     Enable masking (disabling) interrupts during target step/resume.

Debug commands
==============

The following commands give direct access to the core, and are most likely only useful while debugging OpenOCD.

  * arm7_9 write_xpsr <32-BIT VALUE> <0=cpsr, 1=spsr>

     Immediately write either the current program status register (CPSR) or the saved program status register (SPSR), without changing the register cache (as displayed by the reg and armv4_5 reg commands).

  * arm7_9 write_xpsr_im8 <8-BIT VALUE> <ROTATE 4-BIT> <0=CPSR,1=SPSR>

     Write the 8-bit value rotated right by 2*rotate bits, using an immediate write operation (similar to write_xpsr).

  * arm7_9 write_core_reg <NUM> <MODE> <VALUE>

     Write a core register, without changing the register cache (as displayed by the reg and armv4_5 reg commands). The <MODE> argument takes the encoding of the [M4:M0] bits of the PSR.

JTAG commands
=============

  * scan_chain

     Print current scan chain configuration.

  * jtag_reset <TRST> <SRST>

     Toggle reset lines.

  * endstate <TAP_STATE>

     Finish JTAG operations in <TAP_STATE>.

  * runtest <NUM_CYCLES>

     Move to Run-Test/Idle, and execute <NUM_CYCLES>

  * statemove [TAP_STATE]

     Move to current endstate or [TAP_STATE]

  * irscan <DEVICE> <INSTR> [DEV2] [INSTR2] ...

     Execute IR scan <DEVICE> <INSTR> [DEV2] [INSTR2] ...

  * drscan <DEVICE> [DEV2] [VAR2] ...

     Execute DR scan <DEVICE> [DEV2] [VAR2] ...

  * verify_ircapture <enable|disable>

     Verify value captured during Capture-IR. Default is enabled.

  * var <NAME> [NUM_FIELDS|DEL] [SIZE1] ...

     Allocate, display or delete variable <NAME> [NUM_FIELDS|DEL] [SIZE1] ...

  * field <VAR> <FIELD> [VALUE|FLIP] Display/modify variable field <VAR> <FIELD> [VALUE|FLIP].

Target Requests
===============

OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3. See libdcc in the contrib dir for more details.

  * target_request debugmsgs <ENABLE|DISABLE>

     Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.

TFTP
****

If OpenOCD runs on an embedded host(as ZY1000 does), then tftp can be used to access files on PCs(either developer PC or some other PC).

The way this works is to prefix a filename by "/tftp/ip/" and append the tftp path on the tftp server(tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as if the file was hosted on the embedded host.

In order to achieve decent performance, you must choose a tftp server that supports a packet size bigger than the default packet size(512 bytes). There are numerous tftp servers out there(free and commercial) and you will have to do a bit of googling to find something that fits your requirements.

Sample Scripts
**************

This page shows how to use the target library.

The configuration script can be divided in the following section:

  * daemon configuration

  * interface

  * jtag scan chain

  * target configuration

  * flash configuration

Detailed information about each section can be found at OpenOCD configuration.

AT91R40008 example
==================

To start OpenOCD with a target script for the AT91R40008 CPU and reset the CPU upon startup of the OpenOCD daemon.

     openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset

GDB and OpenOCD
***************

OpenOCD complies with the remote gdbserver protocol, and as such can be used to debug remote targets.

Connecting to gdb
=================

Use GDB 6.7 or newer with OpenOCD if you run into trouble. For instance 6.3 has a known bug where it produces bogus memory access errors, which has since been fixed: look up 1836 in http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb

A connection is typically started as follows:

     target remote localhost:3333

This would cause gdb to connect to the gdbserver on the local pc using port 3333.

To see a list of available OpenOCD commands type monitor help on the gdb commandline.

OpenOCD supports the gdb qSupported packet, this enables information to be sent by the gdb server (openocd) to gdb. Typical information includes packet size and device memory map.

Previous versions of OpenOCD required the following gdb options to increase the packet size and speed up gdb communication.

     set remote memory-write-packet-size 1024
     set remote memory-write-packet-size fixed
     set remote memory-read-packet-size 1024
     set remote memory-read-packet-size fixed

This is now handled in the qSupported PacketSize.

Programming using gdb
=====================

By default the target memory map is sent to gdb, this can be disabled by the following OpenOCD config option:

     gdb_memory_map disable

For this to function correctly a valid flash config must also be configured in OpenOCD. For faster performance you should also configure a valid working area.

Informing gdb of the memory map of the target will enable gdb to protect any flash area of the target and use hardware breakpoints by default. This means that the OpenOCD option gdb_breakpoint_override is not required when using a memory map. See gdb_breakpoint_override.

To view the configured memory map in gdb, use the gdb command info mem All other unasigned addresses within gdb are treated as RAM.

GDB 6.8 and higher set any memory area not in the memory map as inaccessible, this can be changed to the old behaviour by using the following gdb command.

     set mem inaccessible-by-default off

If gdb_flash_program enable is also used, gdb will be able to program any flash memory using the vFlash interface.

gdb will look at the target memory map when a load command is given, if any areas to be programmed lie within the target flash area the vFlash packets will be used.

If the target needs configuring before gdb programming, a script can be executed.

     target_script 0 gdb_program_config config.script

To verify any flash programming the gdb command compare-sections can be used.

TCL and OpenOCD
***************

OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting support.

The TCL interpreter can be invoked from the interactive command line, files, and a network port.

The command and file interfaces are fairly straightforward, while the network port is geared toward intergration with external clients. A small example of an external TCL script that can connect to openocd is shown below.

# Simple tcl client to connect to openocd
puts "Use empty line to exit"
set fo [socket 127.0.0.1 6666]
puts -nonewline stdout "> "
flush stdout
while {[gets stdin line] >= 0} {
    if {$line eq {}} break
    puts $fo $line
    flush $fo
    gets $fo line
    puts $line
    puts -nonewline stdout "> "
    flush stdout
}
close $fo

This script can easily be modified to front various GUIs or be a sub component of a larger framework for control and interaction.

TCL scripting API
*****************

API rules

The commands are stateless. E.g. the telnet command line has a concept of currently active target, the Tcl API proc's take this sort of state information as an argument to each proc.

There are three main types of return values: single value, name value pair list and lists.

Name value pair. The proc 'foo' below returns a name/value pair list.

 >  set foo(me)  Duane
 >  set foo(you) Oyvind
 >  set foo(mouse) Micky
 >  set foo(duck) Donald

If one does this:

 >  set foo

The result is:

    me Duane you Oyvind mouse Micky duck Donald

Thus, to get the names of the associative array is easy:

     foreach  { name value }   [set foo]   {
                puts "Name: $name, Value: $value"
     }

Lists returned must be relatively small. Otherwise a range should be passed in to the proc in question.

Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks is the low level API upon which "flash banks" is implemented.

  * ocd_mem2array <VARNAME> <WIDTH> <ADDR> <NELEMS>

     Read memory and return as a TCL array for script processing

  * ocd_array2mem <VARNAME> <WIDTH> <ADDR> <NELEMS>

     Convert a TCL array to memory locations and write the values

  * ocd_flash_banks <DRIVER> <BASE> <SIZE> <CHIP_WIDTH> <BUS_WIDTH> <TARGET> [driver options ...]

     Return information about the flash banks

OpenOCD commands can consist of two words, e.g. "flash banks". The startup.tcl "unknown" proc will translate this into a tcl proc called "flash_banks".

Deprecated/Removed Commands
***************************

Certain OpenOCD commands have been deprecated/removed during the various revisions.

  * load_binary

     use load_image command with same args. See load_image.

  * target

     target no longer take the reset_init, reset_run, run_and_halt, run_and_init. The reset command always does a reset run when passed no arguments.

  * dump_binary

     use dump_image command with same args. See dump_image.

  * flash erase

     use flash erase_sector command with same args. See flash erase_sector.

  * flash write

     use flash write_bank command with same args. See flash write_bank.

  * flash write_binary

     use flash write_bank command with same args. See flash write_bank.

  * arm7_9 fast_writes

     use arm7_9 fast_memory_access command with same args. See arm7_9 fast_memory_access.

  * flash auto_erase

     use flash write_image command passing erase as the first parameter. See flash write_image.

  * daemon_startup

     this config option has been removed, simply adding init and reset halt to the end of your config script will give the same behaviour as using daemon_startup reset and target cortex_m3 little reset_halt 0.

  * arm7_9 sw_bkpts

     On by default. See also gdb_breakpoint_override. See gdb_breakpoint_override.

  * arm7_9 force_hw_bkpts

     Use gdb_breakpoint_override instead. Note that GDB will use hardware breakpoints for flash if the gdb memory map has been set up(default when flash is declared in target configuration). See gdb_breakpoint_override.

  * run_and_halt_time

     This command has been removed for simpler reset behaviour, it can be simulated with the following commands:

          reset run
          sleep 100
          halt

FAQ
***

 1. Why does not backslashes in paths under Windows doesn't work?

     OpenOCD uses Tcl and a backslash is an escape char. Use { and } around Windows filenames.

          > echo \a

          > echo {\a}
          \a
          > echo "\a"

          >

     To

 2. OpenOCD complains about a missing cygwin1.dll.

     Make sure you have Cygwin installed, or at least a version of OpenOCD that claims to come with all the necessary dlls. When using Cygwin, try launching OpenOCD from the Cygwin shell.

 3. I'm trying to set a breakpoint using GDB (or a frontend like Insight or Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".

     GDB issues software breakpoints when a normal breakpoint is requested, or to implement source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t, software breakpoints consume one of the two available hardware breakpoints.

 4. When erasing or writing LPC2000 on-chip flash, the operation fails sometimes and works sometimes fine.

     Make sure the core frequency specified in the flash lpc2000 line matches the clock at the time you're programming the flash. If you've specified the crystal's frequency, make sure the PLL is disabled, if you've specified the full core speed (e.g. 60MHz), make sure the PLL is enabled.

 5. When debugging using an Amontec Chameleon in its JTAG Accelerator configuration, I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed out while waiting for end of scan, rtck was disabled".

     Make sure your PC's parallel port operates in EPP mode. You might have to try several settings in your PC BIOS (ECP, EPP, and different versions of those).

 6. When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse), I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory(): memory read caused data abort".

     The errors are non-fatal, and are the result of GDB trying to trace stack frames beyond the last valid frame. It might be possible to prevent this by setting up a proper "initial" stack frame, if you happen to know what exactly has to be done, feel free to add this here.

 7. I get the following message in the OpenOCD console (or log file): "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".

     This warning doesn't indicate any serious problem, as long as you don't want to debug your core right out of reset. Your .cfg file specified jtag_reset trst_and_srst srst_pulls_trst to tell OpenOCD that either your board, your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals independently. With this setup, it's not possible to halt the core right out of reset, everything else should work fine.

 8. When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be unstable. When single-stepping over large blocks of code, GDB and OpenOCD quit with an error message. Is there a stability issue with OpenOCD?

     No, this is not a stability issue concerning OpenOCD. Most users have solved this issue by simply using a self-powered USB hub, which they connect their Amontec JTAGkey to. Apparently, some computers do not provide a USB power supply stable enough for the Amontec JTAGkey to be operated.

 9. When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned: 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232". What does that mean and what might be the reason for this?

     First of all, the reason might be the USB power supply. Try using a self-powered hub instead of a direct connection to your computer. Secondly, the error code 4 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB chip ran into some sort of error - this points us to a USB problem.

 10. When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054". What does that mean and what might be the reason for this?

     Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB) has closed the connection to OpenOCD. This might be a GDB issue.

 11. In the configuration file in the section where flash device configurations are described, there is a parameter for specifying the clock frequency for LPC2000 internal flash devices (e.g. flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum), which must be specified in kilohertz. However, I do have a quartz crystal of a frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz). Is it possible to specify real numbers for the clock frequency?

     No. The clock frequency specified here must be given as an integral number. However, this clock frequency is used by the In-Application-Programming (IAP) routines of the LPC2000 family only, which seems to be very tolerant concerning the given clock frequency, so a slight difference between the specified clock frequency and the actual clock frequency will not cause any trouble.

 12. Do I have to keep a specific order for the commands in the configuration file?

     Well, yes and no. Commands can be given in arbitrary order, yet the devices listed for the JTAG scan chain must be given in the right order (jtag_device), with the device closest to the TDO-Pin being listed first. In general, whenever objects of the same type exist which require an index number, then these objects must be given in the right order (jtag_devices, targets and flash banks - a target references a jtag_device and a flash bank references a target).

 13. Sometimes my debugging session terminates with an error. When I look into the log file, I can see these error messages: Error: arm7_9_common.c:561 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP

     TODO.

     [file fdl.texi not included]