3 * Copyright 2008,2009 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef INCLUDED_USRP2_IMPL_H
20 #define INCLUDED_USRP2_IMPL_H
22 #include <usrp2/usrp2.h>
23 #include <usrp2/data_handler.h>
24 #include <usrp2_eth_packet.h>
25 #include <boost/scoped_ptr.hpp>
30 #define MAX_SUBPKT_LEN 252
37 class usrp2_tune_result;
41 //! High-level d'board info
44 double freq_min; // Hz
45 double freq_max; // Hz
46 double gain_min; // dB
47 double gain_max; // dB
48 double gain_step_size; // dB
50 db_info() : dbid(-1), freq_min(0), freq_max(0),
51 gain_min(0), gain_max(0), gain_step_size(0) {}
54 class usrp2::impl : private data_handler
56 static const size_t NRIDS = 256;
57 static const size_t NCHANS = 32;
59 eth_buffer *d_eth_buf;
60 std::string d_interface_name;
62 std::string d_addr; // FIXME: use u2_mac_addr_t instead
63 usrp2_thread *d_bg_thread;
64 volatile bool d_bg_running; // TODO: multistate if needed
69 unsigned int d_num_rx_frames;
70 unsigned int d_num_rx_missing;
71 unsigned int d_num_rx_overruns;
72 unsigned int d_num_rx_bytes;
74 unsigned int d_num_enqueued;
75 omni_mutex d_enqueued_mutex;
76 omni_condition d_bg_pending_cond;
78 // all pending_replies are stack allocated, thus no possibility of leaking these
79 pending_reply *d_pending_replies[NRIDS]; // indexed by 8-bit reply id
81 std::vector<ring_sptr> d_channel_rings; // indexed by 5-bit channel number
86 int d_tx_interp; // shadow tx interp
87 int d_rx_decim; // shadow rx decim
90 omni_mutex_lock l(d_enqueued_mutex);
95 omni_mutex_lock l(d_enqueued_mutex);
96 if (--d_num_enqueued == 0)
97 d_bg_pending_cond.signal();
100 static bool parse_mac_addr(const std::string &s, u2_mac_addr_t *p);
101 void init_et_hdrs(u2_eth_packet_t *p, const std::string &dst);
102 void init_etf_hdrs(u2_eth_packet_t *p, const std::string &dst,
103 int word0_flags, int chan, uint32_t timestamp);
105 void init_config_rx_v2_cmd(op_config_rx_v2_cmd *cmd);
106 void init_config_tx_v2_cmd(op_config_tx_v2_cmd *cmd);
107 bool transmit_cmd(void *cmd, size_t len, pending_reply *p, double secs=0.0);
108 virtual data_handler::result operator()(const void *base, size_t len);
109 data_handler::result handle_control_packet(const void *base, size_t len);
110 data_handler::result handle_data_packet(const void *base, size_t len);
115 impl(const std::string &ifc, props *p);
120 std::string mac_addr() const { return d_addr; } // FIXME: convert from u2_mac_addr_t
121 std::string interface_name() const { return d_interface_name; }
125 bool set_rx_gain(double gain);
126 double rx_gain_min() { return d_rx_db_info.gain_min; }
127 double rx_gain_max() { return d_rx_db_info.gain_max; }
128 double rx_gain_db_per_step() { return d_rx_db_info.gain_step_size; }
129 bool set_rx_lo_offset(double frequency);
130 bool set_rx_center_freq(double frequency, tune_result *result);
131 double rx_freq_min() { return d_rx_db_info.freq_min; }
132 double rx_freq_max() { return d_rx_db_info.freq_max; }
133 bool set_rx_decim(int decimation_factor);
134 int rx_decim() { return d_rx_decim; }
135 bool set_rx_scale_iq(int scale_i, int scale_q);
136 bool start_rx_streaming(unsigned int channel, unsigned int items_per_frame);
137 bool rx_samples(unsigned int channel, rx_sample_handler *handler);
138 bool stop_rx_streaming(unsigned int channel);
139 unsigned int rx_overruns() const { return d_num_rx_overruns; }
140 unsigned int rx_missing() const { return d_num_rx_missing; }
144 bool set_tx_gain(double gain);
145 double tx_gain_min() { return d_tx_db_info.gain_min; }
146 double tx_gain_max() { return d_tx_db_info.gain_max; }
147 double tx_gain_db_per_step() { return d_tx_db_info.gain_step_size; }
148 bool set_tx_lo_offset(double frequency);
149 bool set_tx_center_freq(double frequency, tune_result *result);
150 double tx_freq_min() { return d_tx_db_info.freq_min; }
151 double tx_freq_max() { return d_tx_db_info.freq_max; }
152 bool set_tx_interp(int interpolation_factor);
153 int tx_interp() { return d_tx_interp; }
154 void default_tx_scale_iq(int interpolation_factor, int *scale_i, int *scale_q);
155 bool set_tx_scale_iq(int scale_i, int scale_q);
157 bool tx_32fc(unsigned int channel,
158 const std::complex<float> *samples,
160 const tx_metadata *metadata);
162 bool tx_16sc(unsigned int channel,
163 const std::complex<int16_t> *samples,
165 const tx_metadata *metadata);
167 bool tx_raw(unsigned int channel,
168 const uint32_t *items,
170 const tx_metadata *metadata);
174 bool config_mimo(int flags);
175 bool fpga_master_clock_freq(long *freq);
176 bool adc_rate(long *rate);
177 bool dac_rate(long *rate);
178 bool tx_daughterboard_id(int *dbid);
179 bool rx_daughterboard_id(int *dbid);
183 bool burn_mac_addr(const std::string &new_addr);
185 bool sync_every_pps(bool enable);
186 std::vector<uint32_t> peek32(uint32_t addr, uint32_t words);
187 bool poke32(uint32_t addr, const std::vector<uint32_t> &data);
192 #endif /* INCLUDED_USRP2_IMPL_H */