3 * Copyright 2008,2009 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <usrp2/usrp2.h>
24 #include <usrp2/tune_result.h>
25 #include <usrp2/copiers.h>
26 #include <gruel/inet.h>
27 #include <usrp2_types.h>
28 #include "usrp2_impl.h"
29 #include "usrp2_thread.h"
30 #include "eth_buffer.h"
31 #include "pktfilter.h"
41 #define USRP2_IMPL_DEBUG 0
43 #define DEBUG_LOG(x) ::write(2, x, 1)
48 static const int DEFAULT_RX_SCALE = 1024;
52 static const double DEF_CMD_TIMEOUT = 0.1;
55 opcode_to_string(int opcode)
58 case OP_EOP: return "OP_EOP";
59 case OP_ID: return "OP_ID";
60 case OP_ID_REPLY: return "OP_ID_REPLY";
61 case OP_BURN_MAC_ADDR: return "OP_BURN_MAC_ADDR";
62 case OP_READ_TIME: return "OP_READ_TIME";
63 case OP_READ_TIME_REPLY: return "OP_READ_TIME_REPLY";
64 case OP_CONFIG_RX_V2: return "OP_CONFIG_RX_V2";
65 case OP_CONFIG_RX_REPLY_V2: return "OP_CONFIG_RX_REPLY_V2";
66 case OP_CONFIG_TX_V2: return "OP_CONFIG_TX_V2";
67 case OP_CONFIG_TX_REPLY_V2: return "OP_CONFIG_TX_REPLY_V2";
68 case OP_START_RX_STREAMING: return "OP_START_RX_STREAMING";
69 case OP_STOP_RX: return "OP_STOP_RX";
70 case OP_CONFIG_MIMO: return "OP_CONFIG_MIMO";
71 case OP_DBOARD_INFO: return "OP_DBOARD_INFO";
72 case OP_DBOARD_INFO_REPLY: return "OP_DBOARD_INFO_REPLY";
73 case OP_SYNC_TO_PPS: return "OP_SYNC_TO_PPS";
74 case OP_PEEK: return "OP_PEEK";
75 case OP_PEEK_REPLY: return "OP_PEEK_REPLY";
76 case OP_SET_TX_LO_OFFSET: return "OP_SET_TX_LO_OFFSET";
77 case OP_SET_TX_LO_OFFSET_REPLY: return "OP_SET_TX_LO_OFFSET_REPLY";
78 case OP_SET_RX_LO_OFFSET: return "OP_SET_RX_LO_OFFSET";
79 case OP_SET_RX_LO_OFFSET_REPLY: return "OP_SET_RX_LO_OFFSET_REPLY";
80 case OP_SYNC_EVERY_PPS: return "OP_SYNC_EVERY_PPS";
81 case OP_SYNC_EVERY_PPS_REPLY: return "OP_SYNC_EVERY_PPS_REPLY";
85 snprintf(buf, sizeof(buf), "<unknown opcode: %d>", opcode);
92 * \param p points to fixed header
93 * \param payload_len_in_bytes is length of the fixed hdr and the payload
94 * \param[out] items is set to point to the first uint32 item in the payload
95 * \param[out] nitems is set to the number of uint32 items in the payload
96 * \param[out] md is filled in with the parsed metadata from the frame.
99 parse_rx_metadata(void *p, size_t payload_len_in_bytes,
100 uint32_t **items, size_t *nitems_in_uint32s, rx_metadata *md)
102 if (payload_len_in_bytes < sizeof(u2_fixed_hdr_t)) // invalid format
105 // FIXME deal with the fact that (p % 4) == 2
106 //assert((((uintptr_t) p) % 4) == 0); // must be 4-byte aligned
108 u2_fixed_hdr_t *fh = static_cast<u2_fixed_hdr_t *>(p);
110 // FIXME unaligned loads!
111 md->word0 = u2p_word0(fh);
112 md->timestamp = u2p_timestamp(fh);
114 // FIXME when we've got more info
115 // md->start_of_burst = (md->word0 & XXX) != 0;
116 // md->end_of_burst = (md->word0 & XXX) != 0;
117 // md->rx_overrun = (md->word0 & XXX) != 0;
118 md->start_of_burst = 0;
119 md->end_of_burst = 0;
122 *items = (uint32_t *)(&fh[1]);
123 size_t nbytes = payload_len_in_bytes - sizeof(u2_fixed_hdr_t);
124 assert((nbytes % sizeof(uint32_t)) == 0);
125 *nitems_in_uint32s = nbytes / sizeof(uint32_t);
131 usrp2::impl::impl(const std::string &ifc, props *p, size_t rx_bufsize)
132 : d_eth_buf(new eth_buffer(rx_bufsize)), d_interface_name(ifc), d_pf(0), d_bg_thread(0),
133 d_bg_running(false), d_rx_seqno(-1), d_tx_seqno(0), d_next_rid(0),
134 d_num_rx_frames(0), d_num_rx_missing(0), d_num_rx_overruns(0), d_num_rx_bytes(0),
135 d_num_enqueued(0), d_enqueued_mutex(), d_bg_pending_cond(&d_enqueued_mutex),
136 d_channel_rings(NCHANS), d_tx_interp(0), d_rx_decim(0), d_dont_enqueue(true)
138 if (!d_eth_buf->open(ifc, htons(U2_ETHERTYPE)))
139 throw std::runtime_error("Unable to register USRP2 protocol");
143 // Create a packet filter for U2_ETHERTYPE packets sourced from target USRP2
144 u2_mac_addr_t usrp_mac;
145 parse_mac_addr(d_addr, &usrp_mac);
146 d_pf = pktfilter::make_ethertype_inbound_target(U2_ETHERTYPE, (const unsigned char*)&(usrp_mac.addr));
147 if (!d_pf || !d_eth_buf->attach_pktfilter(d_pf))
148 throw std::runtime_error("Unable to attach packet filter.");
150 if (USRP2_IMPL_DEBUG)
151 std::cerr << "usrp2 constructor: using USRP2 at " << d_addr << std::endl;
153 memset(d_pending_replies, 0, sizeof(d_pending_replies));
155 d_bg_thread = new usrp2_thread(this);
156 d_bg_thread->start();
158 // In case the USRP2 was left streaming RX
159 // FIXME: only one channel right now
160 stop_rx_streaming(0);
162 if (!dboard_info()) // we're hosed
163 throw std::runtime_error("Unable to retrieve daughterboard info");
168 tx_daughterboard_id(&dbid);
169 fprintf(stderr, "Tx dboard 0x%x\n", dbid);
170 fprintf(stderr, " freq_min = %g\n", tx_freq_min());
171 fprintf(stderr, " freq_max = %g\n", tx_freq_max());
172 fprintf(stderr, " gain_min = %g\n", tx_gain_min());
173 fprintf(stderr, " gain_max = %g\n", tx_gain_max());
174 fprintf(stderr, " gain_db_per_step = %g\n", tx_gain_db_per_step());
176 rx_daughterboard_id(&dbid);
177 fprintf(stderr, "Rx dboard 0x%x\n", dbid);
178 fprintf(stderr, " freq_min = %g\n", rx_freq_min());
179 fprintf(stderr, " freq_max = %g\n", rx_freq_max());
180 fprintf(stderr, " gain_min = %g\n", rx_gain_min());
181 fprintf(stderr, " gain_max = %g\n", rx_gain_max());
182 fprintf(stderr, " gain_db_per_step = %g\n", rx_gain_db_per_step());
185 // Ensure any custom values in hardware are cleared
187 std::cerr << "usrp2::ctor reset_db failed\n";
189 // default gains to mid point
190 if (!set_tx_gain((tx_gain_min() + tx_gain_max()) / 2))
191 std::cerr << "usrp2::ctor set_tx_gain failed\n";
193 if (!set_rx_gain((rx_gain_min() + rx_gain_max()) / 2))
194 std::cerr << "usrp2::ctor set_rx_gain failed\n";
196 // default interp and decim
197 if (!set_tx_interp(12))
198 std::cerr << "usrp2::ctor set_tx_interp failed\n";
200 if (!set_rx_decim(12))
201 std::cerr << "usrp2::ctor set_rx_decim failed\n";
203 // set workable defaults for scaling
204 if (!set_rx_scale_iq(DEFAULT_RX_SCALE, DEFAULT_RX_SCALE))
205 std::cerr << "usrp2::ctor set_rx_scale_iq failed\n";
211 d_bg_thread = 0; // thread class deletes itself
216 if (USRP2_IMPL_DEBUG) {
217 std::cerr << std::endl
218 << "usrp2 destructor: received " << d_num_rx_frames
219 << " frames, with " << d_num_rx_missing << " lost ("
220 << (d_num_rx_frames == 0 ? 0 : (int)(100.0*d_num_rx_missing/d_num_rx_frames))
221 << "%), totaling " << d_num_rx_bytes
222 << " bytes" << std::endl;
227 usrp2::impl::parse_mac_addr(const std::string &s, u2_mac_addr_t *p)
229 p->addr[0] = 0x00; // Matt's IAB
241 return sscanf(s.c_str(), "%hhx:%hhx", &p->addr[4], &p->addr[5]) == 2;
244 return sscanf(s.c_str(), "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
245 &p->addr[0], &p->addr[1], &p->addr[2],
246 &p->addr[3], &p->addr[4], &p->addr[5]) == 6;
253 usrp2::impl::init_et_hdrs(u2_eth_packet_t *p, const std::string &dst)
255 p->ehdr.ethertype = htons(U2_ETHERTYPE);
256 parse_mac_addr(dst, &p->ehdr.dst);
257 memcpy(&p->ehdr.src, d_eth_buf->mac(), 6);
258 p->thdr.flags = 0; // FIXME transport header values?
259 p->thdr.seqno = d_tx_seqno++;
264 usrp2::impl::init_etf_hdrs(u2_eth_packet_t *p, const std::string &dst,
265 int word0_flags, int chan, uint32_t timestamp)
267 init_et_hdrs(p, dst);
268 u2p_set_word0(&p->fixed, word0_flags, chan);
269 u2p_set_timestamp(&p->fixed, timestamp);
271 if (chan == CONTROL_CHAN) { // no sequence numbers, back it out
278 usrp2::impl::init_config_rx_v2_cmd(op_config_rx_v2_cmd *cmd)
280 memset(cmd, 0, sizeof(*cmd));
281 init_etf_hdrs(&cmd->h, d_addr, 0, CONTROL_CHAN, -1);
282 cmd->op.opcode = OP_CONFIG_RX_V2;
283 cmd->op.len = sizeof(cmd->op);
284 cmd->op.rid = d_next_rid++;
285 cmd->eop.opcode = OP_EOP;
286 cmd->eop.len = sizeof(cmd->eop);
290 usrp2::impl::init_config_tx_v2_cmd(op_config_tx_v2_cmd *cmd)
292 memset(cmd, 0, sizeof(*cmd));
293 init_etf_hdrs(&cmd->h, d_addr, 0, CONTROL_CHAN, -1);
294 cmd->op.opcode = OP_CONFIG_TX_V2;
295 cmd->op.len = sizeof(cmd->op);
296 cmd->op.rid = d_next_rid++;
297 cmd->eop.opcode = OP_EOP;
298 cmd->eop.len = sizeof(cmd->eop);
303 usrp2::impl::transmit_cmd(void *cmd, size_t len)
305 return d_eth_buf->tx_frame(cmd, len) == eth_buffer::EB_OK;
309 usrp2::impl::transmit_cmd_and_wait(void *cmd, size_t len, pending_reply *p, double secs)
311 d_pending_replies[p->rid()] = p;
313 if (!transmit_cmd(cmd, len)){
314 d_pending_replies[p->rid()] = 0;
318 int res = p->wait_for_completion(secs);
319 d_pending_replies[p->rid()] = 0;
323 // ----------------------------------------------------------------
324 // Background loop: received packet demuxing
325 // ----------------------------------------------------------------
328 usrp2::impl::stop_bg()
330 d_bg_running = false;
331 d_bg_pending_cond.signal();
334 d_bg_thread->join(&dummy_status);
338 usrp2::impl::bg_loop()
341 while(d_bg_running) {
343 // Receive available frames from ethernet buffer. Handler will
344 // process control frames, enqueue data packets in channel
345 // rings, and signal blocked API threads
346 int res = d_eth_buf->rx_frames(this, 100); // FIXME magic timeout
347 if (res == eth_buffer::EB_ERROR)
350 // Wait for user API thread(s) to process all enqueued packets.
351 // The channel ring thread that decrements d_num_enqueued to zero
352 // will signal this thread to continue.
354 omni_mutex_lock l(d_enqueued_mutex);
355 while(d_num_enqueued > 0 && d_bg_running)
356 d_bg_pending_cond.wait();
359 d_bg_running = false;
363 // passed to eth_buffer::rx_frames
366 usrp2::impl::operator()(const void *base, size_t len)
368 u2_eth_samples_t *pkt = (u2_eth_samples_t *)base;
370 // FIXME unaligned load!
371 int chan = u2p_chan(&pkt->hdrs.fixed);
373 if (chan == CONTROL_CHAN) { // control packets
375 return handle_control_packet(base, len);
377 else { // data packets
379 if (d_dont_enqueue) // toss packet
380 return data_handler::RELEASE;
382 return handle_data_packet(base, len);
389 usrp2::impl::handle_control_packet(const void *base, size_t len)
391 // point to beginning of payload (subpackets)
392 unsigned char *p = (unsigned char *)base + sizeof(u2_eth_packet_t);
394 // FIXME (p % 4) == 2. Not good. Must watch for unaligned loads.
396 // FIXME iterate over payload, handling more than a single subpacket.
399 unsigned int oplen = p[1];
400 unsigned int rid = p[2];
402 pending_reply *rp = d_pending_replies[rid];
404 unsigned int buflen = rp->len();
405 if (oplen != buflen) {
406 std::cerr << "usrp2: mismatched command reply length (expected: "
407 << buflen << " got: " << oplen << "). "
408 << "op = " << opcode_to_string(opcode) << std::endl;
411 // Copy reply into caller's buffer
412 memcpy(rp->buffer(), p, std::min(oplen, buflen));
413 rp->notify_completion();
414 d_pending_replies[rid] = 0;
415 return data_handler::RELEASE;
418 // TODO: handle unsolicited, USRP2 initiated, or late replies
420 return data_handler::RELEASE;
424 usrp2::impl::handle_data_packet(const void *base, size_t len)
426 u2_eth_samples_t *pkt = (u2_eth_samples_t *)base;
428 d_num_rx_bytes += len;
430 /* --- FIXME start of fake transport layer handler --- */
432 if (d_rx_seqno != -1) {
433 int expected_seqno = (d_rx_seqno + 1) & 0xFF;
434 int seqno = pkt->hdrs.thdr.seqno;
436 if (seqno != expected_seqno) {
437 ::write(2, "S", 1); // missing sequence number
438 int missing = seqno - expected_seqno;
443 d_num_rx_missing += missing;
447 d_rx_seqno = pkt->hdrs.thdr.seqno;
449 /* --- end of fake transport layer handler --- */
451 // FIXME unaligned load!
452 unsigned int chan = u2p_chan(&pkt->hdrs.fixed);
455 omni_mutex_lock l(d_channel_rings_mutex);
457 if (!d_channel_rings[chan]) {
459 return data_handler::RELEASE; // discard packet, no channel handler
462 // Strip off ethernet header and transport header and enqueue the rest
464 size_t offset = offsetof(u2_eth_samples_t, hdrs.fixed);
465 if (d_channel_rings[chan]->enqueue(&pkt->hdrs.fixed, len-offset)) {
468 return data_handler::KEEP; // channel ring runner will mark frame done
472 return data_handler::RELEASE; // discard, no room in channel ring
474 return data_handler::RELEASE;
479 // ----------------------------------------------------------------
481 // ----------------------------------------------------------------
484 usrp2::impl::set_rx_gain(double gain)
486 op_config_rx_v2_cmd cmd;
487 op_config_rx_reply_v2_t reply;
489 init_config_rx_v2_cmd(&cmd);
490 cmd.op.valid = htons(CFGV_GAIN);
491 cmd.op.gain = htons(u2_double_to_fxpt_gain(gain));
493 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
494 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
497 bool success = (ntohx(reply.ok) == 1);
502 usrp2::impl::set_rx_lo_offset(double frequency)
507 memset(&cmd, 0, sizeof(cmd));
508 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
509 cmd.op.opcode = OP_SET_RX_LO_OFFSET;
510 cmd.op.len = sizeof(cmd.op);
511 cmd.op.rid = d_next_rid++;
513 u2_fxpt_freq_t fxpt = u2_double_to_fxpt_freq(frequency);
514 cmd.op.freq_hi = htonl(u2_fxpt_freq_hi(fxpt));
515 cmd.op.freq_lo = htonl(u2_fxpt_freq_lo(fxpt));
517 cmd.eop.opcode = OP_EOP;
518 cmd.eop.len = sizeof(cmd.eop);
520 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
521 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
524 bool success = (ntohx(reply.ok) == 1);
529 usrp2::impl::set_rx_center_freq(double frequency, tune_result *result)
531 op_config_rx_v2_cmd cmd;
532 op_config_rx_reply_v2_t reply;
534 init_config_rx_v2_cmd(&cmd);
535 cmd.op.valid = htons(CFGV_FREQ);
536 u2_fxpt_freq_t fxpt = u2_double_to_fxpt_freq(frequency);
537 cmd.op.freq_hi = htonl(u2_fxpt_freq_hi(fxpt));
538 cmd.op.freq_lo = htonl(u2_fxpt_freq_lo(fxpt));
540 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
541 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
544 bool success = (ntohx(reply.ok) == 1);
545 if (result && success) {
546 result->baseband_freq =
547 u2_fxpt_freq_to_double(
548 u2_fxpt_freq_from_hilo(ntohl(reply.baseband_freq_hi),
549 ntohl(reply.baseband_freq_lo)));
552 u2_fxpt_freq_to_double(
553 u2_fxpt_freq_from_hilo(ntohl(reply.ddc_freq_hi),
554 ntohl(reply.ddc_freq_lo)));
556 result->residual_freq =
557 u2_fxpt_freq_to_double(
558 u2_fxpt_freq_from_hilo(ntohl(reply.residual_freq_hi),
559 ntohl(reply.residual_freq_lo)));
561 result->spectrum_inverted = (bool)(ntohx(reply.inverted) == 1);
568 usrp2::impl::set_rx_decim(int decimation_factor)
570 op_config_rx_v2_cmd cmd;
571 op_config_rx_reply_v2_t reply;
573 init_config_rx_v2_cmd(&cmd);
574 cmd.op.valid = htons(CFGV_INTERP_DECIM);
575 cmd.op.decim = htonl(decimation_factor);
577 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
578 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
581 bool success = (ntohx(reply.ok) == 1);
583 d_rx_decim = decimation_factor;
588 usrp2::impl::set_rx_scale_iq(int scale_i, int scale_q)
590 op_config_rx_v2_cmd cmd;
591 op_config_rx_reply_v2_t reply;
593 init_config_rx_v2_cmd(&cmd);
594 cmd.op.valid = htons(CFGV_SCALE_IQ);
595 cmd.op.scale_iq = htonl(((scale_i & 0xffff) << 16) | (scale_q & 0xffff));
597 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
598 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
601 bool success = (ntohx(reply.ok) == 1);
606 usrp2::impl::start_rx_streaming(unsigned int channel, unsigned int items_per_frame)
608 if (channel > MAX_CHAN) {
609 std::cerr << "usrp2: invalid channel number (" << channel
614 if (channel > 0) { // until firmware supports multiple streams
615 std::cerr << "usrp2: channel " << channel
616 << " not implemented" << std::endl;
621 omni_mutex_lock l(d_channel_rings_mutex);
622 if (d_channel_rings[channel]) {
623 std::cerr << "usrp2: channel " << channel
624 << " already streaming" << std::endl;
628 if (items_per_frame == 0)
629 items_per_frame = U2_MAX_SAMPLES; // minimize overhead
631 op_start_rx_streaming_cmd cmd;
634 memset(&cmd, 0, sizeof(cmd));
635 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
636 cmd.op.opcode = OP_START_RX_STREAMING;
637 cmd.op.len = sizeof(cmd.op);
638 cmd.op.rid = d_next_rid++;
639 cmd.op.items_per_frame = htonl(items_per_frame);
640 cmd.eop.opcode = OP_EOP;
641 cmd.eop.len = sizeof(cmd.eop);
643 d_dont_enqueue = false;
644 bool success = false;
645 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
646 success = transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT);
647 success = success && (ntohx(reply.ok) == 1);
650 d_channel_rings[channel] = ring_sptr(new ring(d_eth_buf->max_frames()));
652 d_dont_enqueue = true;
654 //fprintf(stderr, "usrp2::start_rx_streaming: success = %d\n", success);
660 usrp2::impl::stop_rx_streaming(unsigned int channel)
662 if (channel > MAX_CHAN) {
663 std::cerr << "usrp2: invalid channel number (" << channel
668 if (channel > 0) { // until firmware supports multiple streams
669 std::cerr << "usrp2: channel " << channel
670 << " not implemented" << std::endl;
674 d_dont_enqueue = true; // no new samples
675 flush_rx_samples(channel); // dump any we may already have
681 omni_mutex_lock l(d_channel_rings_mutex);
683 memset(&cmd, 0, sizeof(cmd));
684 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
685 cmd.op.opcode = OP_STOP_RX;
686 cmd.op.len = sizeof(cmd.op);
687 cmd.op.rid = d_next_rid++;
688 cmd.eop.opcode = OP_EOP;
689 cmd.eop.len = sizeof(cmd.eop);
691 bool success = false;
692 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
693 success = transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT);
694 success = success && (ntohx(reply.ok) == 1);
695 d_channel_rings[channel].reset();
696 //fprintf(stderr, "usrp2::stop_rx_streaming: success = %d\n", success);
702 usrp2::impl::rx_samples(unsigned int channel, rx_sample_handler *handler)
704 if (channel > MAX_CHAN) {
705 std::cerr << "usrp2: invalid channel (" << channel
706 << " )" << std::endl;
711 std::cerr << "usrp2: channel " << channel
712 << " not implemented" << std::endl;
716 ring_sptr rp = d_channel_rings[channel];
718 std::cerr << "usrp2: channel " << channel
719 << " not receiving" << std::endl;
723 // Wait for frames available in channel ring
725 rp->wait_for_not_empty();
728 // Iterate through frames and present to user
730 size_t frame_len_in_bytes;
731 while (rp->dequeue(&p, &frame_len_in_bytes)) {
732 uint32_t *items; // points to beginning of data items
733 size_t nitems_in_uint32s;
735 if (!parse_rx_metadata(p, frame_len_in_bytes, &items, &nitems_in_uint32s, &md))
738 bool want_more = (*handler)(items, nitems_in_uint32s, &md);
739 d_eth_buf->release_frame(p);
750 usrp2::impl::flush_rx_samples(unsigned int channel)
752 if (channel > MAX_CHAN) {
753 std::cerr << "usrp2: invalid channel (" << channel
754 << " )" << std::endl;
759 std::cerr << "usrp2: channel " << channel
760 << " not implemented" << std::endl;
764 ring_sptr rp = d_channel_rings[channel];
769 // Iterate through frames and drop them
771 size_t frame_len_in_bytes;
772 while (rp->dequeue(&p, &frame_len_in_bytes)) {
773 d_eth_buf->release_frame(p);
779 // ----------------------------------------------------------------
781 // ----------------------------------------------------------------
784 usrp2::impl::set_tx_gain(double gain)
786 op_config_tx_v2_cmd cmd;
787 op_config_tx_reply_v2_t reply;
789 init_config_tx_v2_cmd(&cmd);
790 cmd.op.valid = htons(CFGV_GAIN);
791 cmd.op.gain = htons(u2_double_to_fxpt_gain(gain));
793 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
794 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
797 bool success = (ntohx(reply.ok) == 1);
802 usrp2::impl::set_tx_lo_offset(double frequency)
807 memset(&cmd, 0, sizeof(cmd));
808 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
809 cmd.op.opcode = OP_SET_TX_LO_OFFSET;
810 cmd.op.len = sizeof(cmd.op);
811 cmd.op.rid = d_next_rid++;
813 u2_fxpt_freq_t fxpt = u2_double_to_fxpt_freq(frequency);
814 cmd.op.freq_hi = htonl(u2_fxpt_freq_hi(fxpt));
815 cmd.op.freq_lo = htonl(u2_fxpt_freq_lo(fxpt));
817 cmd.eop.opcode = OP_EOP;
818 cmd.eop.len = sizeof(cmd.eop);
820 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
821 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
824 bool success = (ntohx(reply.ok) == 1);
829 usrp2::impl::set_tx_center_freq(double frequency, tune_result *result)
831 op_config_tx_v2_cmd cmd;
832 op_config_tx_reply_v2_t reply;
834 init_config_tx_v2_cmd(&cmd);
835 cmd.op.valid = htons(CFGV_FREQ);
836 u2_fxpt_freq_t fxpt = u2_double_to_fxpt_freq(frequency);
837 cmd.op.freq_hi = htonl(u2_fxpt_freq_hi(fxpt));
838 cmd.op.freq_lo = htonl(u2_fxpt_freq_lo(fxpt));
840 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
841 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
844 bool success = (ntohx(reply.ok) == 1);
845 if (result && success) {
846 result->baseband_freq =
847 u2_fxpt_freq_to_double(
848 u2_fxpt_freq_from_hilo(ntohl(reply.baseband_freq_hi),
849 ntohl(reply.baseband_freq_lo)));
852 u2_fxpt_freq_to_double(
853 u2_fxpt_freq_from_hilo(ntohl(reply.duc_freq_hi),
854 ntohl(reply.duc_freq_lo)));
856 result->residual_freq =
857 u2_fxpt_freq_to_double(
858 u2_fxpt_freq_from_hilo(ntohl(reply.residual_freq_hi),
859 ntohl(reply.residual_freq_lo)));
861 result->spectrum_inverted = (bool)(ntohx(reply.inverted) == 1);
868 usrp2::impl::set_tx_interp(int interpolation_factor)
870 op_config_tx_v2_cmd cmd;
871 op_config_tx_reply_v2_t reply;
873 init_config_tx_v2_cmd(&cmd);
874 cmd.op.valid = htons(CFGV_INTERP_DECIM);
875 cmd.op.interp = htonl(interpolation_factor);
877 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
878 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
881 bool success = (ntohx(reply.ok) == 1);
883 d_tx_interp = interpolation_factor;
885 // Auto-set TX scaling based on interpolation rate
886 int scale_i, scale_q;
887 default_tx_scale_iq(d_tx_interp, &scale_i, &scale_q);
888 return set_tx_scale_iq(scale_i, scale_q);
895 usrp2::impl::default_tx_scale_iq(int interpolation_factor, int *scale_i, int *scale_q)
897 // Calculate CIC interpolation (i.e., without halfband interpolators)
898 int i = interpolation_factor;
904 // Calculate dsp_core_tx gain absent scale multipliers
905 float gain = (1.65*i*i*i)/(4096*pow(2, ceil(log2(i*i*i))));
907 // Calculate closest multiplier constant to reverse gain
908 int scale = (int)rint(1.0/gain);
909 // fprintf(stderr, "if=%i i=%i gain=%f scale=%i\n", interpolation_factor, i, gain, scale);
911 // Both I and Q are identical in this case
919 usrp2::impl::set_tx_scale_iq(int scale_i, int scale_q)
921 op_config_tx_v2_cmd cmd;
922 op_config_tx_reply_v2_t reply;
924 init_config_tx_v2_cmd(&cmd);
925 cmd.op.valid = htons(CFGV_SCALE_IQ);
926 cmd.op.scale_iq = htonl(((scale_i & 0xffff) << 16) | (scale_q & 0xffff));
928 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
929 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
932 bool success = (ntohx(reply.ok) == 1);
937 usrp2::impl::tx_32fc(unsigned int channel,
938 const std::complex<float> *samples,
940 const tx_metadata *metadata)
942 uint32_t items[nsamples];
943 copy_host_32fc_to_u2_16sc(nsamples, samples, items);
944 return tx_raw(channel, items, nsamples, metadata);
948 usrp2::impl::tx_16sc(unsigned int channel,
949 const std::complex<int16_t> *samples,
951 const tx_metadata *metadata)
953 #ifdef WORDS_BIGENDIAN
955 // Already binary equivalent to 16-bit I/Q on the wire.
956 // No conversion required.
958 assert(sizeof(samples[0]) == sizeof(uint32_t));
959 return tx_raw(channel, (const uint32_t *) samples, nsamples, metadata);
963 uint32_t items[nsamples];
964 copy_host_16sc_to_u2_16sc(nsamples, samples, items);
965 return tx_raw(channel, items, nsamples, metadata);
971 usrp2::impl::tx_raw(unsigned int channel,
972 const uint32_t *items,
974 const tx_metadata *metadata)
979 // FIXME can't deal with nitems < U2_MIN_SAMPLES (will be fixed in VRT)
980 // FIXME need to check the MTU instead of assuming 1500 bytes
982 // fragment as necessary then fire away
984 size_t nframes = (nitems + U2_MAX_SAMPLES - 1) / U2_MAX_SAMPLES;
985 size_t last_frame = nframes - 1;
986 u2_eth_packet_t hdrs;
989 for (size_t fn = 0; fn < nframes; fn++){
990 uint32_t timestamp = 0;
994 timestamp = metadata->timestamp;
995 if (metadata->send_now)
996 flags |= U2P_TX_IMMEDIATE;
997 if (metadata->start_of_burst)
998 flags |= U2P_TX_START_OF_BURST;
1001 flags |= U2P_TX_IMMEDIATE;
1003 if (fn == last_frame){
1004 if (metadata->end_of_burst)
1005 flags |= U2P_TX_END_OF_BURST;
1008 init_etf_hdrs(&hdrs, d_addr, flags, channel, timestamp);
1010 // Avoid short packet by splitting last two packets if reqd
1012 if ((nitems - n) > U2_MAX_SAMPLES && (nitems - n) < (U2_MAX_SAMPLES + U2_MIN_SAMPLES))
1013 i = (nitems - n) / 2;
1015 i = std::min((size_t) U2_MAX_SAMPLES, nitems - n);
1018 iov[0].iov_base = &hdrs;
1019 iov[0].iov_len = sizeof(hdrs);
1020 iov[1].iov_base = const_cast<uint32_t *>(&items[n]);
1021 iov[1].iov_len = i * sizeof(uint32_t);
1023 size_t total = iov[0].iov_len + iov[1].iov_len;
1025 fprintf(stderr, "usrp2::tx_raw: FIXME: short packet: %zd items (%zd bytes)\n", i, total);
1027 if (d_eth_buf->tx_framev(iov, 2) != eth_buffer::EB_OK){
1037 // ----------------------------------------------------------------
1039 // ----------------------------------------------------------------
1042 usrp2::impl::config_mimo(int flags)
1044 op_config_mimo_cmd cmd;
1047 memset(&cmd, 0, sizeof(cmd));
1048 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1049 cmd.op.opcode = OP_CONFIG_MIMO;
1050 cmd.op.len = sizeof(cmd.op);
1051 cmd.op.rid = d_next_rid++;
1052 cmd.op.flags = flags;
1053 cmd.eop.opcode = OP_EOP;
1054 cmd.eop.len = sizeof(cmd.eop);
1056 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1057 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
1060 return ntohx(reply.ok) == 1;
1064 usrp2::impl::fpga_master_clock_freq(long *freq)
1066 *freq = 100000000L; // 100 MHz
1071 usrp2::impl::adc_rate(long *rate)
1073 return fpga_master_clock_freq(rate);
1077 usrp2::impl::dac_rate(long *rate)
1079 return fpga_master_clock_freq(rate);
1083 usrp2::impl::tx_daughterboard_id(int *dbid)
1085 *dbid = d_tx_db_info.dbid;
1090 usrp2::impl::rx_daughterboard_id(int *dbid)
1092 *dbid = d_rx_db_info.dbid;
1097 // ----------------------------------------------------------------
1098 // low-level commands
1099 // ----------------------------------------------------------------
1102 usrp2::impl::burn_mac_addr(const std::string &new_addr)
1104 op_burn_mac_addr_cmd cmd;
1107 memset(&cmd, 0, sizeof(cmd));
1108 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1109 cmd.op.opcode = OP_BURN_MAC_ADDR;
1110 cmd.op.len = sizeof(cmd.op);
1111 cmd.op.rid = d_next_rid++;
1112 if (!parse_mac_addr(new_addr, &cmd.op.addr))
1115 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1116 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, 4*DEF_CMD_TIMEOUT))
1119 bool success = (ntohx(reply.ok) == 1);
1124 fill_dboard_info(db_info *dst, const u2_db_info_t *src)
1126 dst->dbid = ntohl(src->dbid);
1129 u2_fxpt_freq_to_double(u2_fxpt_freq_from_hilo(ntohl(src->freq_min_hi),
1130 ntohl(src->freq_min_lo)));
1132 u2_fxpt_freq_to_double(u2_fxpt_freq_from_hilo(ntohl(src->freq_max_hi),
1133 ntohl(src->freq_max_lo)));
1135 dst->gain_min = u2_fxpt_gain_to_double(ntohs(src->gain_min));
1136 dst->gain_max = u2_fxpt_gain_to_double(ntohs(src->gain_max));
1137 dst->gain_step_size = u2_fxpt_gain_to_double(ntohs(src->gain_step_size));
1141 usrp2::impl::dboard_info()
1143 op_dboard_info_cmd cmd;
1144 op_dboard_info_reply_t reply;
1146 memset(&cmd, 0, sizeof(cmd));
1147 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1148 cmd.op.opcode = OP_DBOARD_INFO;
1149 cmd.op.len = sizeof(cmd.op);
1150 cmd.op.rid = d_next_rid++;
1151 cmd.eop.opcode = OP_EOP;
1152 cmd.eop.len = sizeof(cmd.eop);
1154 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1155 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
1158 bool success = (ntohx(reply.ok) == 1);
1160 fill_dboard_info(&d_tx_db_info, &reply.tx_db_info);
1161 fill_dboard_info(&d_rx_db_info, &reply.rx_db_info);
1168 usrp2::impl::sync_to_pps()
1173 memset(&cmd, 0, sizeof(cmd));
1174 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1175 cmd.op.opcode = OP_SYNC_TO_PPS;
1176 cmd.op.len = sizeof(cmd.op);
1177 cmd.op.rid = d_next_rid++;
1178 cmd.eop.opcode = OP_EOP;
1179 cmd.eop.len = sizeof(cmd.eop);
1181 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1182 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
1185 return ntohx(reply.ok) == 1;
1189 usrp2::impl::sync_every_pps(bool enable)
1194 memset(&cmd, 0, sizeof(cmd));
1195 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1196 cmd.op.opcode = OP_SYNC_EVERY_PPS;
1197 cmd.op.len = sizeof(cmd.op);
1198 cmd.op.rid = d_next_rid++;
1199 cmd.op.ok = enable ? 1 : 0;
1200 cmd.eop.opcode = OP_EOP;
1201 cmd.eop.len = sizeof(cmd.eop);
1203 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1204 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
1207 return ntohx(reply.ok) == 1;
1210 std::vector<uint32_t>
1211 usrp2::impl::peek32(uint32_t addr, uint32_t words)
1213 std::vector<uint32_t> result; // zero sized on error return
1214 // fprintf(stderr, "usrp2::peek: addr=%08X words=%u\n", addr, words);
1216 if (addr % 4 != 0) {
1217 fprintf(stderr, "usrp2::peek: addr (=%08X) must be 32-bit word aligned\n", addr);
1225 op_generic_t *reply;
1227 int wlen = sizeof(uint32_t);
1228 int rlen = sizeof(op_generic_t);
1229 size_t bytes = words*wlen;
1231 memset(&cmd, 0, sizeof(cmd));
1232 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1233 cmd.op.opcode = OP_PEEK;
1234 cmd.op.len = sizeof(cmd.op);
1235 cmd.op.rid = d_next_rid++;
1236 cmd.eop.opcode = OP_EOP;
1237 cmd.eop.len = sizeof(cmd.eop);
1239 cmd.op.addr = htonl(addr);
1240 cmd.op.bytes = htonl(bytes);
1242 reply = (op_generic_t *)malloc(rlen+bytes);
1243 pending_reply p(cmd.op.rid, reply, rlen+bytes);
1244 if (transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) {
1245 uint32_t nwords = (reply->len-rlen)/sizeof(uint32_t);
1246 uint32_t *data = (uint32_t *)(reply+rlen/wlen);
1247 for (unsigned int i = 0; i < nwords; i++)
1248 result.push_back(ntohl(data[i]));
1256 usrp2::impl::poke32(uint32_t addr, const std::vector<uint32_t> &data)
1258 if (addr % 4 != 0) {
1259 fprintf(stderr, "usrp2::poke32: addr (=%08X) must be 32-bit word aligned\n", addr);
1263 int plen = sizeof(op_poke_cmd);
1264 int wlen = sizeof(uint32_t);
1265 int max_words = (MAX_SUBPKT_LEN-plen)/wlen;
1266 int words = data.size();
1268 if (words > max_words) {
1269 fprintf(stderr, "usrp2::poke32: write size (=%u) exceeds maximum of %u words\n",
1274 //fprintf(stderr, "usrp2::poke32: addr=%08X words=%u\n", addr, words);
1282 // Allocate, clear, and initialize command packet
1283 int bytes = words*wlen;
1284 int l = plen+bytes+sizeof(*eop); // op_poke_cmd+data+eop
1285 cmd = (op_poke_cmd *)malloc(l);
1286 //fprintf(stderr, "cmd=%p l=%i\n", cmd, l);
1288 init_etf_hdrs(&cmd->h, d_addr, 0, CONTROL_CHAN, -1);
1289 cmd->op.opcode = OP_POKE;
1290 cmd->op.len = sizeof(cmd->op)+bytes;
1291 cmd->op.rid = d_next_rid++;
1292 cmd->op.addr = htonl(addr);
1294 // Copy data from vector into packet space
1295 uint32_t *dest = (uint32_t *)((uint8_t *)cmd+plen);
1296 for (int i = 0; i < words; i++) {
1297 //fprintf(stderr, "%03i@%p\n", i, dest);
1298 *dest++ = htonl(data[i]);
1301 // Write end-of-packet subpacket
1302 eop = (op_generic_t *)dest;
1303 eop->opcode = OP_EOP;
1304 eop->len = sizeof(*eop);
1305 //fprintf(stderr, "eop=%p len=%i\n", eop, eop->len);
1307 // Send command to device and retrieve reply
1310 pending_reply p(cmd->op.rid, &reply, sizeof(reply));
1311 if (transmit_cmd_and_wait(cmd, l, &p, DEF_CMD_TIMEOUT))
1312 ok = (ntohx(reply.ok) == 1);
1319 usrp2::impl::reset_db()
1324 memset(&cmd, 0, sizeof(cmd));
1325 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1326 cmd.op.opcode = OP_RESET_DB;
1327 cmd.op.len = sizeof(cmd.op);
1328 cmd.op.rid = d_next_rid++;
1329 cmd.eop.opcode = OP_EOP;
1330 cmd.eop.len = sizeof(cmd.eop);
1332 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1333 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
1336 bool success = (ntohx(reply.ok) == 1);
1340 bool usrp2::impl::set_gpio_ddr(int bank, uint16_t value, uint16_t mask)
1342 if (bank != GPIO_TX_BANK && bank != GPIO_RX_BANK) {
1343 fprintf(stderr, "set_gpio_ddr: bank must be one of GPIO_RX_BANK or GPIO_TX_BANK\n");
1350 memset(&cmd, 0, sizeof(cmd));
1351 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1352 cmd.op.opcode = OP_GPIO_SET_DDR;
1353 cmd.op.len = sizeof(cmd.op);
1354 cmd.op.rid = d_next_rid++;
1355 cmd.op.bank = static_cast<uint8_t>(bank);
1356 cmd.op.value = htons(value);
1357 cmd.op.mask = htons(mask);
1358 cmd.eop.opcode = OP_EOP;
1359 cmd.eop.len = sizeof(cmd.eop);
1361 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1362 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
1365 bool success = (ntohx(reply.ok) == 1);
1369 bool usrp2::impl::set_gpio_sels(int bank, std::string sels)
1371 if (bank != GPIO_TX_BANK && bank != GPIO_RX_BANK) {
1372 fprintf(stderr, "set_gpio_ddr: bank must be one of GPIO_RX_BANK or GPIO_TX_BANK\n");
1376 if (sels.size() != 16) {
1377 fprintf(stderr, "set_gpio_sels: sels must be exactly 16 bytes\n");
1381 op_gpio_set_sels_cmd cmd;
1384 memset(&cmd, 0, sizeof(cmd));
1385 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1386 cmd.op.opcode = OP_GPIO_SET_SELS;
1387 cmd.op.len = sizeof(cmd.op);
1388 cmd.op.rid = d_next_rid++;
1389 cmd.op.bank = static_cast<uint8_t>(bank);
1390 memcpy(&cmd.op.sels, sels.c_str(), 16);
1391 cmd.eop.opcode = OP_EOP;
1392 cmd.eop.len = sizeof(cmd.eop);
1394 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1395 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
1398 bool success = (ntohx(reply.ok) == 1);
1402 bool usrp2::impl::write_gpio(int bank, uint16_t value, uint16_t mask)
1404 if (bank != GPIO_TX_BANK && bank != GPIO_RX_BANK) {
1405 fprintf(stderr, "set_gpio_ddr: bank must be one of GPIO_RX_BANK or GPIO_TX_BANK\n");
1412 memset(&cmd, 0, sizeof(cmd));
1413 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1414 cmd.op.opcode = OP_GPIO_WRITE;
1415 cmd.op.len = sizeof(cmd.op);
1416 cmd.op.rid = d_next_rid++;
1417 cmd.op.bank = static_cast<uint8_t>(bank);
1418 cmd.op.value = htons(value);
1419 cmd.op.mask = htons(mask);
1420 cmd.eop.opcode = OP_EOP;
1421 cmd.eop.len = sizeof(cmd.eop);
1423 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1424 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
1427 bool success = (ntohx(reply.ok) == 1);
1431 bool usrp2::impl::read_gpio(int bank, uint16_t *value)
1433 if (bank != GPIO_TX_BANK && bank != GPIO_RX_BANK) {
1434 fprintf(stderr, "set_gpio_ddr: bank must be one of GPIO_RX_BANK or GPIO_TX_BANK\n");
1439 op_gpio_read_reply_t reply;
1441 memset(&cmd, 0, sizeof(cmd));
1442 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1443 cmd.op.opcode = OP_GPIO_READ;
1444 cmd.op.len = sizeof(cmd.op);
1445 cmd.op.rid = d_next_rid++;
1446 cmd.op.bank = static_cast<uint8_t>(bank);
1447 cmd.op.value = 0; // not used
1448 cmd.op.mask = 0; // not used
1449 cmd.eop.opcode = OP_EOP;
1450 cmd.eop.len = sizeof(cmd.eop);
1452 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1453 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
1456 bool success = (ntohx(reply.ok) == 1);
1457 if (success && (value != NULL))
1458 *value = ntohs(reply.value);
1463 bool usrp2::impl::enable_gpio_streaming(int bank, int enable)
1465 if (bank != GPIO_RX_BANK) {
1466 fprintf(stderr, "enable_gpio_streaming: only RX streaming is currently implemented\n");
1470 if ((enable & ~0x03) != 0) {
1471 fprintf(stderr, "enable_gpio_streaming: invalid enable format\n");
1478 memset(&cmd, 0, sizeof(cmd));
1479 init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
1480 cmd.op.opcode = OP_GPIO_STREAM;
1481 cmd.op.len = sizeof(cmd.op);
1482 cmd.op.rid = d_next_rid++;
1483 cmd.op.bank = static_cast<uint8_t>(bank);
1484 cmd.op.value = htons((uint16_t)enable);
1485 cmd.op.mask = 0; // not used
1486 cmd.eop.opcode = OP_EOP;
1487 cmd.eop.len = sizeof(cmd.eop);
1489 pending_reply p(cmd.op.rid, &reply, sizeof(reply));
1490 if (!transmit_cmd_and_wait(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
1493 bool success = (ntohx(reply.ok) == 1);
1497 } // namespace usrp2