2 #(parameter INPUTW = 16,
4 parameter OUTPUTW = 16)
11 input [INPUTW-1:0] data_i,
14 output reg [OUTPUTW-1:0] integ_o
17 wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i};
18 reg [ACCUMW-1:0] accum;
20 always @(posedge clk_i)
29 integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW];
33 accum <= accum + data_ext;
35 always @(posedge clk_i)
38 endmodule // integrate