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   1 #
   2 # Copyright 2008 Ettus Research LLC
   3 #
   4 # This file is part of GNU Radio
   5 #
   6 # GNU Radio is free software; you can redistribute it and/or modify
   7 # it under the terms of the GNU General Public License as published by
   8 # the Free Software Foundation; either version 3, or (at your option)
   9 # any later version.
  10 #
  11 # GNU Radio is distributed in the hope that it will be useful,
  12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 # GNU General Public License for more details.
  15 #
  16 # You should have received a copy of the GNU General Public License
  17 # along with GNU Radio; see the file COPYING.  If not, write to
  18 # the Free Software Foundation, Inc., 51 Franklin Street,
  19 # Boston, MA 02110-1301, USA.
  20 #
  21
  22 ##################################################
  23 # xtclsh Shell and tcl Script Path
  24 ##################################################
  25 #XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
  26 XTCLSH := xtclsh
  27 ISE_HELPER := ../tcl/ise_helper.tcl
  28
  29 ##################################################
  30 # Project Setup
  31 ##################################################
  32 BUILD_DIR := build/
  33 export TOP_MODULE := u2_rev3
  34 export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
  35
  36 ##################################################
  37 # Project Properties
  38 ##################################################
  39 export PROJECT_PROPERTIES := \
  40 family Spartan3 \
  41 device xc3s2000 \
  42 package fg456 \
  43 speed -5 \
  44 top_level_module_type "HDL" \
  45 synthesis_tool "XST (VHDL/Verilog)" \
  46 simulator "ISE Simulator (VHDL/Verilog)" \
  47 "Preferred Language" "Verilog" \
  48 "Enable Message Filtering" FALSE \
  49 "Display Incremental Messages" FALSE
  50
  51 ##################################################
  52 # Sources
  53 ##################################################
  54 export SOURCE_ROOT := ../../../
  55 export SOURCES := \
  56 control_lib/CRC16_D16.v \
  57 control_lib/atr_controller.v \
  58 control_lib/bin2gray.v \
  59 control_lib/buffer_int.v \
  60 control_lib/buffer_pool.v \
  61 control_lib/cascadefifo2.v \
  62 control_lib/dcache.v \
  63 control_lib/decoder_3_8.v \
  64 control_lib/dpram32.v \
  65 control_lib/fifo_2clock.v \
  66 control_lib/fifo_2clock_casc.v \
  67 control_lib/gray2bin.v \
  68 control_lib/gray_send.v \
  69 control_lib/icache.v \
  70 control_lib/longfifo.v \
  71 control_lib/mux4.v \
  72 control_lib/mux8.v \
  73 control_lib/nsgpio.v \
  74 control_lib/ram_2port.v \
  75 control_lib/ram_harv_cache.v \
  76 control_lib/ram_loader.v \
  77 control_lib/setting_reg.v \
  78 control_lib/settings_bus.v \
  79 control_lib/shortfifo.v \
  80 control_lib/medfifo.v \
  81 control_lib/srl.v \
  82 control_lib/system_control.v \
  83 control_lib/wb_1master.v \
  84 control_lib/wb_readback_mux.v \
  85 control_lib/simple_uart.v \
  86 control_lib/simple_uart_tx.v \
  87 control_lib/simple_uart_rx.v \
  88 control_lib/oneshot_2clk.v \
  89 control_lib/sd_spi.v \
  90 control_lib/sd_spi_wb.v \
  91 control_lib/wb_bridge_16_32.v \
  92 coregen/fifo_xlnx_2Kx36_2clk.v \
  93 coregen/fifo_xlnx_2Kx36_2clk.xco \
  94 coregen/fifo_xlnx_512x36_2clk.v \
  95 coregen/fifo_xlnx_512x36_2clk.xco \
  96 eth/mac_rxfifo_int.v \
  97 eth/mac_txfifo_int.v \
  98 eth/rtl/verilog/Clk_ctrl.v \
  99 eth/rtl/verilog/MAC_rx.v \
 100 eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
 101 eth/rtl/verilog/MAC_rx/CRC_chk.v \
 102 eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
 103 eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
 104 eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
 105 eth/rtl/verilog/MAC_top.v \
 106 eth/rtl/verilog/MAC_tx.v \
 107 eth/rtl/verilog/MAC_tx/CRC_gen.v \
 108 eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
 109 eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
 110 eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
 111 eth/rtl/verilog/MAC_tx/Random_gen.v \
 112 eth/rtl/verilog/Phy_int.v \
 113 eth/rtl/verilog/RMON.v \
 114 eth/rtl/verilog/RMON/RMON_addr_gen.v \
 115 eth/rtl/verilog/RMON/RMON_ctrl.v \
 116 eth/rtl/verilog/Reg_int.v \
 117 eth/rtl/verilog/eth_miim.v \
 118 eth/rtl/verilog/flow_ctrl_rx.v \
 119 eth/rtl/verilog/flow_ctrl_tx.v \
 120 eth/rtl/verilog/miim/eth_clockgen.v \
 121 eth/rtl/verilog/miim/eth_outputcontrol.v \
 122 eth/rtl/verilog/miim/eth_shiftreg.v \
 123 extram/wb_zbt16_b.v \
 124 opencores/8b10b/decode_8b10b.v \
 125 opencores/8b10b/encode_8b10b.v \
 126 opencores/aemb/rtl/verilog/aeMB_bpcu.v \
 127 opencores/aemb/rtl/verilog/aeMB_core_BE.v \
 128 opencores/aemb/rtl/verilog/aeMB_ctrl.v \
 129 opencores/aemb/rtl/verilog/aeMB_edk32.v \
 130 opencores/aemb/rtl/verilog/aeMB_ibuf.v \
 131 opencores/aemb/rtl/verilog/aeMB_regf.v \
 132 opencores/aemb/rtl/verilog/aeMB_xecu.v \
 133 opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
 134 opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
 135 opencores/i2c/rtl/verilog/i2c_master_defines.v \
 136 opencores/i2c/rtl/verilog/i2c_master_top.v \
 137 opencores/i2c/rtl/verilog/timescale.v \
 138 opencores/simple_pic/rtl/simple_pic.v \
 139 opencores/spi/rtl/verilog/spi_clgen.v \
 140 opencores/spi/rtl/verilog/spi_defines.v \
 141 opencores/spi/rtl/verilog/spi_shift.v \
 142 opencores/spi/rtl/verilog/spi_top.v \
 143 opencores/spi/rtl/verilog/timescale.v \
 144 sdr_lib/acc.v \
 145 sdr_lib/add2.v \
 146 sdr_lib/add2_and_round.v \
 147 sdr_lib/add2_and_round_reg.v \
 148 sdr_lib/add2_reg.v \
 149 sdr_lib/cic_dec_shifter.v \
 150 sdr_lib/cic_decim.v \
 151 sdr_lib/cic_int_shifter.v \
 152 sdr_lib/cic_interp.v \
 153 sdr_lib/cic_strober.v \
 154 sdr_lib/clip.v \
 155 sdr_lib/clip_reg.v \
 156 sdr_lib/cordic.v \
 157 sdr_lib/cordic_z24.v \
 158 sdr_lib/cordic_stage.v \
 159 sdr_lib/dsp_core_tx.v \
 160 sdr_lib/hb_dec.v \
 161 sdr_lib/hb_interp.v \
 162 sdr_lib/integrate.v \
 163 sdr_lib/round.v \
 164 sdr_lib/round_reg.v \
 165 sdr_lib/rx_control.v \
 166 sdr_lib/rx_dcoffset.v \
 167 sdr_lib/sign_extend.v \
 168 sdr_lib/small_hb_dec.v \
 169 sdr_lib/small_hb_int.v \
 170 sdr_lib/tx_control.v \
 171 serdes/serdes.v \
 172 serdes/serdes_fc_rx.v \
 173 serdes/serdes_fc_tx.v \
 174 serdes/serdes_rx.v \
 175 serdes/serdes_tx.v \
 176 timing/time_receiver.v \
 177 timing/time_sender.v \
 178 timing/time_sync.v \
 179 timing/timer.v \
 180 top/u2_core/u2_core.v \
 181 top/u2_rev3/u2_rev3.ucf \
 182 top/u2_rev3/u2_rev3.v \
 183 top/u2_rev3_iad/dsp_core_rx.v
 184
 185 ##################################################
 186 # Process Properties
 187 ##################################################
 188 export SYNTHESIZE_PROPERTIES := \
 189 "Number of Clock Buffers" 6 \
 190 "Pack I/O Registers into IOBs" Yes \
 191 "Optimization Effort" High \
 192 "Optimize Instantiated Primitives" TRUE \
 193 "Register Balancing" Yes \
 194 "Use Clock Enable" Auto \
 195 "Use Synchronous Reset" Auto \
 196 "Use Synchronous Set" Auto
 197
 198 export TRANSLATE_PROPERTIES := \
 199 "Macro Search Path" "$(shell pwd)/../../coregen/"
 200
 201 export MAP_PROPERTIES := \
 202 "Allow Logic Optimization Across Hierarchy" TRUE \
 203 "Map to Input Functions" 4 \
 204 "Optimization Strategy (Cover Mode)" Speed \
 205 "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
 206 "Perform Timing-Driven Packing and Placement" TRUE \
 207 "Map Effort Level" High \
 208 "Extra Effort" Normal \
 209 "Combinatorial Logic Optimization" TRUE \
 210 "Register Duplication" TRUE
 211
 212 export PLACE_ROUTE_PROPERTIES := \
 213 "Place & Route Effort Level (Overall)" High
 214
 215 export STATIC_TIMING_PROPERTIES := \
 216 "Number of Paths in Error/Verbose Report" 10 \
 217 "Report Type" "Error Report"
 218
 219 export GEN_PROG_FILE_PROPERTIES := \
 220 "Configuration Rate" 6 \
 221 "Create Binary Configuration File" TRUE \
 222 "Done (Output Events)" 5 \
 223 "Enable Bitstream Compression" TRUE \
 224 "Enable Outputs (Output Events)" 6
 225
 226 export SIM_MODEL_PROPERTIES := ""
 227
 228 ##################################################
 229 # Make Options
 230 ##################################################
 231 all:
 232         @echo make proj, check, synth, bin, testbench, or clean
 233
 234 proj:
 235         PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
 236
 237 check:
 238         PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
 239
 240 synth:
 241         PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
 242
 243 bin:
 244         PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
 245
 246 testbench:
 247         iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v
 248
 249 clean:
 250         rm -rf $(BUILD_DIR)
 251         rm -f dsp_core_tb
 252         rm -f *.lx2
 253         rm -f *.dat
 254         rm -f *.vcd